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[PULL 06/60] target/ppc: Tidy POWER book4 SPR registration
From: |
Daniel Henrique Barboza |
Subject: |
[PULL 06/60] target/ppc: Tidy POWER book4 SPR registration |
Date: |
Fri, 7 Jul 2023 08:30:14 -0300 |
From: Nicholas Piggin <npiggin@gmail.com>
POWER book4 (implementation-specific) SPRs are sometimes in their own
functions, but in other cases are mixed with architected SPRs. Do some
spring cleaning on these.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-ID: <20230625120317.13877-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
target/ppc/cpu_init.c | 82 +++++++++++++++++++++++++++++--------------
1 file changed, 55 insertions(+), 27 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index aeff71d063..dc93581dd3 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5370,31 +5370,6 @@ static void register_book3s_ids_sprs(CPUPPCState *env)
&spr_read_generic, SPR_NOACCESS,
&spr_read_generic, NULL,
0x00000000);
- spr_register_hv(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_TSCR, "TSCR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic32,
- 0x00000000);
- spr_register_hv(env, SPR_HMER, "HMER",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_hmer,
- 0x00000000);
- spr_register_hv(env, SPR_HMEER, "HMEER",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register_hv(env, SPR_TFMR, "TFMR",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
spr_register_hv(env, SPR_LPIDR, "LPIDR",
SPR_NOACCESS, SPR_NOACCESS,
SPR_NOACCESS, SPR_NOACCESS,
@@ -5656,14 +5631,60 @@ static void register_power8_ic_sprs(CPUPPCState *env)
#endif
}
+/* SPRs specific to IBM POWER CPUs */
+static void register_power_common_book4_sprs(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_hv(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_TSCR, "TSCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic32,
+ 0x00000000);
+ spr_register_hv(env, SPR_HMER, "HMER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_hmer,
+ 0x00000000);
+ spr_register_hv(env, SPR_HMEER, "HMEER",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register_hv(env, SPR_TFMR, "TFMR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+#endif
+}
+
+static void register_power9_book4_sprs(CPUPPCState *env)
+{
+ /* Add a number of P9 book4 registers */
+ register_power_common_book4_sprs(env);
+#if !defined(CONFIG_USER_ONLY)
+ spr_register_kvm(env, SPR_WORT, "WORT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_WORT, 0);
+#endif
+}
+
static void register_power8_book4_sprs(CPUPPCState *env)
{
/* Add a number of P8 book4 registers */
+ register_power_common_book4_sprs(env);
#if !defined(CONFIG_USER_ONLY)
spr_register_kvm(env, SPR_ACOP, "ACOP",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_ACOP, 0);
+ /* PID is only in BookE in ISA v2.07 */
spr_register_kvm(env, SPR_BOOKS_PID, "PID",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pidr,
@@ -5679,10 +5700,12 @@ static void register_power7_book4_sprs(CPUPPCState *env)
{
/* Add a number of P7 book4 registers */
#if !defined(CONFIG_USER_ONLY)
+ register_power_common_book4_sprs(env);
spr_register_kvm(env, SPR_ACOP, "ACOP",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_ACOP, 0);
+ /* PID is only in BookE in ISA v2.06 */
spr_register_kvm(env, SPR_BOOKS_PID, "PID",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic32,
@@ -5716,6 +5739,11 @@ static void register_power9_mmu_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x0000000000000000);
+ /* PID is part of the BookS ISA from v3.0 */
+ spr_register_kvm(env, SPR_BOOKS_PID, "PID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pidr,
+ KVM_REG_PPC_PID, 0);
#endif
}
@@ -6269,7 +6297,7 @@ static void init_proc_POWER9(CPUPPCState *env)
register_power8_dpdes_sprs(env);
register_vtb_sprs(env);
register_power8_ic_sprs(env);
- register_power8_book4_sprs(env);
+ register_power9_book4_sprs(env);
register_power8_rpr_sprs(env);
register_power9_mmu_sprs(env);
@@ -6462,7 +6490,7 @@ static void init_proc_POWER10(CPUPPCState *env)
register_power8_dpdes_sprs(env);
register_vtb_sprs(env);
register_power8_ic_sprs(env);
- register_power8_book4_sprs(env);
+ register_power9_book4_sprs(env);
register_power8_rpr_sprs(env);
register_power9_mmu_sprs(env);
register_power10_hash_sprs(env);
--
2.41.0
- [PULL 00/60] ppc queue, Daniel Henrique Barboza, 2023/07/07
- [PULL 01/60] pnv/psi: Allow access to PSI registers through xscom, Daniel Henrique Barboza, 2023/07/07
- [PULL 02/60] target/ppc: Make HDECR underflow edge triggered, Daniel Henrique Barboza, 2023/07/07
- [PULL 03/60] hw/ppc: Fix clock update drift, Daniel Henrique Barboza, 2023/07/07
- [PULL 05/60] mv64361: Add dummy gigabit ethernet PHY access registers, Daniel Henrique Barboza, 2023/07/07
- [PULL 06/60] target/ppc: Tidy POWER book4 SPR registration,
Daniel Henrique Barboza <=
- [PULL 04/60] target/ppc: Only generate decodetree files when TCG is enabled, Daniel Henrique Barboza, 2023/07/07
- [PULL 07/60] target/ppc: Add TFMR SPR implementation with read and write helpers, Daniel Henrique Barboza, 2023/07/07
- [PULL 08/60] sungem: Add WOL MMIO, Daniel Henrique Barboza, 2023/07/07
- [PULL 09/60] target/ppc: Fix icount access for some hypervisor instructions, Daniel Henrique Barboza, 2023/07/07
- [PULL 10/60] tests/avocado: record_replay test for ppc powernv machine, Daniel Henrique Barboza, 2023/07/07
- [PULL 11/60] pnv/xive2: Allow indirect TIMA accesses of all sizes, Daniel Henrique Barboza, 2023/07/07
- [PULL 12/60] target/ppc: Remove some superfluous parentheses, Daniel Henrique Barboza, 2023/07/07
- [PULL 13/60] target/ppc: Remove unneeded parameter from powerpc_reset_wakeup(), Daniel Henrique Barboza, 2023/07/07
- [PULL 14/60] target/ppc: Move common check in exception handlers to a function, Daniel Henrique Barboza, 2023/07/07
- [PULL 15/60] target/ppc: Remove some more local CPUState variables only used once, Daniel Henrique Barboza, 2023/07/07