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[RFC PATCH v4 23/44] target/loongarch: Implement vsllwil vextl
From: |
Song Gao |
Subject: |
[RFC PATCH v4 23/44] target/loongarch: Implement vsllwil vextl |
Date: |
Tue, 25 Apr 2023 15:02:27 +0800 |
This patch includes:
- VSLLWIL.{H.B/W.H/D.W};
- VSLLWIL.{HU.BU/WU.HU/DU.WU};
- VEXTL.Q.D, VEXTL.QU.DU.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/disas.c | 9 +++++
target/loongarch/helper.h | 9 +++++
target/loongarch/insn_trans/trans_lsx.c.inc | 21 +++++++++++
target/loongarch/insns.decode | 9 +++++
target/loongarch/lsx_helper.c | 41 +++++++++++++++++++++
5 files changed, 89 insertions(+)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index f7d0fb4441..087cac10ad 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1139,3 +1139,12 @@ INSN_LSX(vrotri_b, vv_i)
INSN_LSX(vrotri_h, vv_i)
INSN_LSX(vrotri_w, vv_i)
INSN_LSX(vrotri_d, vv_i)
+
+INSN_LSX(vsllwil_h_b, vv_i)
+INSN_LSX(vsllwil_w_h, vv_i)
+INSN_LSX(vsllwil_d_w, vv_i)
+INSN_LSX(vextl_q_d, vv)
+INSN_LSX(vsllwil_hu_bu, vv_i)
+INSN_LSX(vsllwil_wu_hu, vv_i)
+INSN_LSX(vsllwil_du_wu, vv_i)
+INSN_LSX(vextl_qu_du, vv)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 617c579592..e98f7c3e6f 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -352,3 +352,12 @@ DEF_HELPER_3(vmskgez_b, void, env, i32, i32)
DEF_HELPER_3(vmsknz_b, void, env, i32,i32)
DEF_HELPER_FLAGS_4(vnori_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
+
+DEF_HELPER_4(vsllwil_h_b, void, env, i32, i32, i32)
+DEF_HELPER_4(vsllwil_w_h, void, env, i32, i32, i32)
+DEF_HELPER_4(vsllwil_d_w, void, env, i32, i32, i32)
+DEF_HELPER_3(vextl_q_d, void, env, i32, i32)
+DEF_HELPER_4(vsllwil_hu_bu, void, env, i32, i32, i32)
+DEF_HELPER_4(vsllwil_wu_hu, void, env, i32, i32, i32)
+DEF_HELPER_4(vsllwil_du_wu, void, env, i32, i32, i32)
+DEF_HELPER_3(vextl_qu_du, void, env, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc
b/target/loongarch/insn_trans/trans_lsx.c.inc
index ad8f32ed18..037c742aa4 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -39,6 +39,18 @@ static bool gen_vv(DisasContext *ctx, arg_vv *a,
return true;
}
+static bool gen_vv_i(DisasContext *ctx, arg_vv_i *a,
+ void (*func)(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 vd = tcg_constant_i32(a->vd);
+ TCGv_i32 vj = tcg_constant_i32(a->vj);
+ TCGv_i32 imm = tcg_constant_i32(a->imm);
+
+ CHECK_SXE;
+ func(cpu_env, vd, vj, imm);
+ return true;
+}
+
static bool gvec_vvv(DisasContext *ctx, arg_vvv *a, MemOp mop,
void (*func)(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t))
@@ -2966,3 +2978,12 @@ TRANS(vrotri_b, gvec_vv_i, MO_8, tcg_gen_gvec_rotri)
TRANS(vrotri_h, gvec_vv_i, MO_16, tcg_gen_gvec_rotri)
TRANS(vrotri_w, gvec_vv_i, MO_32, tcg_gen_gvec_rotri)
TRANS(vrotri_d, gvec_vv_i, MO_64, tcg_gen_gvec_rotri)
+
+TRANS(vsllwil_h_b, gen_vv_i, gen_helper_vsllwil_h_b)
+TRANS(vsllwil_w_h, gen_vv_i, gen_helper_vsllwil_w_h)
+TRANS(vsllwil_d_w, gen_vv_i, gen_helper_vsllwil_d_w)
+TRANS(vextl_q_d, gen_vv, gen_helper_vextl_q_d)
+TRANS(vsllwil_hu_bu, gen_vv_i, gen_helper_vsllwil_hu_bu)
+TRANS(vsllwil_wu_hu, gen_vv_i, gen_helper_vsllwil_wu_hu)
+TRANS(vsllwil_du_wu, gen_vv_i, gen_helper_vsllwil_du_wu)
+TRANS(vextl_qu_du, gen_vv, gen_helper_vextl_qu_du)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 7c0b0c4ac8..23dd338026 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -839,3 +839,12 @@ vrotri_b 0111 00101010 00000 01 ... ..... .....
@vv_ui3
vrotri_h 0111 00101010 00000 1 .... ..... ..... @vv_ui4
vrotri_w 0111 00101010 00001 ..... ..... ..... @vv_ui5
vrotri_d 0111 00101010 0001 ...... ..... ..... @vv_ui6
+
+vsllwil_h_b 0111 00110000 10000 01 ... ..... ..... @vv_ui3
+vsllwil_w_h 0111 00110000 10000 1 .... ..... ..... @vv_ui4
+vsllwil_d_w 0111 00110000 10001 ..... ..... ..... @vv_ui5
+vextl_q_d 0111 00110000 10010 00000 ..... ..... @vv
+vsllwil_hu_bu 0111 00110000 11000 01 ... ..... ..... @vv_ui3
+vsllwil_wu_hu 0111 00110000 11000 1 .... ..... ..... @vv_ui4
+vsllwil_du_wu 0111 00110000 11001 ..... ..... ..... @vv_ui5
+vextl_qu_du 0111 00110000 11010 00000 ..... ..... @vv
diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c
index ff00d60ab8..de86f41cce 100644
--- a/target/loongarch/lsx_helper.c
+++ b/target/loongarch/lsx_helper.c
@@ -793,3 +793,44 @@ void HELPER(vnori_b)(void *vd, void *vj, uint64_t imm,
uint32_t v)
Vd->B(i) = ~(Vj->B(i) | (uint8_t)imm);
}
}
+
+#define VSLLWIL(NAME, BIT, E1, E2) \
+void HELPER(NAME)(CPULoongArchState *env, \
+ uint32_t vd, uint32_t vj, uint32_t imm) \
+{ \
+ int i; \
+ VReg temp; \
+ VReg *Vd = &(env->fpr[vd].vreg); \
+ VReg *Vj = &(env->fpr[vj].vreg); \
+ typedef __typeof(temp.E1(0)) TD; \
+ \
+ temp.D(0) = 0; \
+ temp.D(1) = 0; \
+ for (i = 0; i < LSX_LEN/BIT; i++) { \
+ temp.E1(i) = (TD)Vj->E2(i) << (imm % BIT); \
+ } \
+ *Vd = temp; \
+}
+
+void HELPER(vextl_q_d)(CPULoongArchState *env, uint32_t vd, uint32_t vj)
+{
+ VReg *Vd = &(env->fpr[vd].vreg);
+ VReg *Vj = &(env->fpr[vj].vreg);
+
+ Vd->Q(0) = int128_makes64(Vj->D(0));
+}
+
+void HELPER(vextl_qu_du)(CPULoongArchState *env, uint32_t vd, uint32_t vj)
+{
+ VReg *Vd = &(env->fpr[vd].vreg);
+ VReg *Vj = &(env->fpr[vj].vreg);
+
+ Vd->Q(0) = int128_make64(Vj->D(0));
+}
+
+VSLLWIL(vsllwil_h_b, 16, H, B)
+VSLLWIL(vsllwil_w_h, 32, W, H)
+VSLLWIL(vsllwil_d_w, 64, D, W)
+VSLLWIL(vsllwil_hu_bu, 16, UH, UB)
+VSLLWIL(vsllwil_wu_hu, 32, UW, UH)
+VSLLWIL(vsllwil_du_wu, 64, UD, UW)
--
2.31.1
- [RFC PATCH v4 08/44] target/loongarch: Implement vhaddw/vhsubw, (continued)
- [RFC PATCH v4 08/44] target/loongarch: Implement vhaddw/vhsubw, Song Gao, 2023/04/25
- [RFC PATCH v4 12/44] target/loongarch: Implement vadda, Song Gao, 2023/04/25
- [RFC PATCH v4 10/44] target/loongarch: Implement vavg/vavgr, Song Gao, 2023/04/25
- [RFC PATCH v4 14/44] target/loongarch: Implement vmul/vmuh/vmulw{ev/od}, Song Gao, 2023/04/25
- [RFC PATCH v4 16/44] target/loongarch: Implement vdiv/vmod, Song Gao, 2023/04/25
- [RFC PATCH v4 15/44] target/loongarch: Implement vmadd/vmsub/vmaddw{ev/od}, Song Gao, 2023/04/25
- [RFC PATCH v4 18/44] target/loongarch: Implement vexth, Song Gao, 2023/04/25
- [RFC PATCH v4 13/44] target/loongarch: Implement vmax/vmin, Song Gao, 2023/04/25
- [RFC PATCH v4 21/44] target/loongarch: Implement LSX logic instructions, Song Gao, 2023/04/25
- [RFC PATCH v4 19/44] target/loongarch: Implement vsigncov, Song Gao, 2023/04/25
- [RFC PATCH v4 23/44] target/loongarch: Implement vsllwil vextl,
Song Gao <=
- [RFC PATCH v4 24/44] target/loongarch: Implement vsrlr vsrar, Song Gao, 2023/04/25
- [RFC PATCH v4 26/44] target/loongarch: Implement vsrlrn vsrarn, Song Gao, 2023/04/25
- [RFC PATCH v4 29/44] target/loongarch: Implement vclo vclz, Song Gao, 2023/04/25
- [RFC PATCH v4 27/44] target/loongarch: Implement vssrln vssran, Song Gao, 2023/04/25
- [RFC PATCH v4 30/44] target/loongarch: Implement vpcnt, Song Gao, 2023/04/25
- [RFC PATCH v4 31/44] target/loongarch: Implement vbitclr vbitset vbitrev, Song Gao, 2023/04/25
- [RFC PATCH v4 35/44] target/loongarch: Implement vseq vsle vslt, Song Gao, 2023/04/25
- [RFC PATCH v4 32/44] target/loongarch: Implement vfrstp, Song Gao, 2023/04/25
- [RFC PATCH v4 33/44] target/loongarch: Implement LSX fpu arith instructions, Song Gao, 2023/04/25
- [RFC PATCH v4 28/44] target/loongarch: Implement vssrlrn vssrarn, Song Gao, 2023/04/25