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Re: [PATCH 02/13] hw/ide/via: Implement ISA IRQ routing


From: Bernhard Beschow
Subject: Re: [PATCH 02/13] hw/ide/via: Implement ISA IRQ routing
Date: Mon, 24 Apr 2023 07:50:35 +0000


Am 22. April 2023 19:21:12 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>:
>On Sat, 22 Apr 2023, Bernhard Beschow wrote:
>> Am 22. April 2023 17:23:56 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>:
>>> On Sat, 22 Apr 2023, Bernhard Beschow wrote:
>>>> The VIA south bridge allows the legacy IDE interrupts to be routed to four
>>>> different ISA interrupts. This can be configured through the 0x4a register 
>>>> in
>>>> the PCI configuration space of the ISA function. The default routing 
>>>> matches
>>>> the legacy ISA IRQs, that is 14 and 15.
>>> 
>>> On VT8231 0x4a is PCI Master Arbitration Control, IDE interrupt Routing is 
>>> 0x4c and only documents 14/15 as valid values.
>> 
>> In the datasheet titled "VT8231 South Bridge", preliminary revision 0.8, 
>> Oct. 29, 1999, page 60, the "IDE Interrupt Routing" register is located at 
>> offset 0x4a and offers the same four interrupts in the same order as in the 
>> code. Are we looking at the same datasheet?
>
>Apparently not. The one I have says: Revision 2.32, May 10, 2004. Looks more 
>authorative than a preliminary one.

Indeed. I've updated my copy of the datasheet.

>
>>> Not sure any guest would actually change this or 0x4a and if that could 
>>> cause problems but you may need to handle this somehow. (Apart from testing 
>>> with MorphOS with -kernel you should really be testing with pegasos2.rom 
>>> with MorphOS and Linux, e.g. Debian 8.11 netinstall iso is known to boot.)
>> 
>> I've tested extensively with an x86 Linux guest on my pc-via branch which 
>> worked flawlessly.
>
>That does not substitute testing Linux on pegasos2 though becuase there are 
>some hacks in Linux kernel to handle some pecularities of the pegasos2 
>including via ide on that machine and that can only be fully tested with 
>pegasos2.rom and PPC Linux.

I'll try to find the Debian ISO to test with pegasos2.rom.

>
>> As mentioned in the commit message the default routing of the chipset 
>> matches legacy behavior, that is interrupts 14 and 15. This is reflected by 
>> assigning [0x4a] = 4 in the code and that is how the code behaved before.
>
>And that's the only allowed value on VT8231, other bits are listed as reserved 
>so I wonder if we want to model this at all if no guest is touching it anyway. 
>So you could also just drop that part and keep it hard mapped to 14-15 as it 
>is now, mentioning the config reg in a comment if we ever find a guest that 
>needs it.

I see it now. I'll use hardcoded IRQs 14 and 15 then.

Best regards,
Bernhard

>
>Regards,
>BALATON Zoltan



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