Re: Error : "cxl_pci 0000:0d:00.0: Failed to get interrupt for event Info log"

[Jonathan Cameron]

On Fri, 21 Apr 2023 19:14:05 +0530
RAGHU H <raghuhack78@gmail.com> wrote:

> Hi Jonathan,
> 
> The log is from the upstream version.
> I have your repo, I can work on it if you provide some basic details
> like the commit ID.

I tag the latest branch with cxl-YYYY-MM-DD 
https://gitlab.com/jic23/qemu cxl-2023-04-19

should work for you.

> 
> Regards
> Raghu
> 
> On Fri, Apr 21, 2023 at 6:05 PM Jonathan Cameron
> <Jonathan.Cameron@huawei.com> wrote:
> >
> > On Thu, 20 Apr 2023 18:07:40 +0530
> > RAGHU H <raghuhack78@gmail.com> wrote:
> >  
> > > Hello,
> > >
> > > I am using qemu config listed in CXL documentation to emulate CXL device
> > >
> > >
> > > -object 
> > > memory-backend-file,id=cxl-mem1,share=on,mem-path=/tmp/cxltest.raw,size=256M
> > > \
> > > -object 
> > > memory-backend-file,id=cxl-mem2,share=on,mem-path=/tmp/cxltest2.raw,size=256M
> > > \
> > > -object 
> > > memory-backend-file,id=cxl-mem3,share=on,mem-path=/tmp/cxltest3.raw,size=256M
> > > \
> > > -object 
> > > memory-backend-file,id=cxl-mem4,share=on,mem-path=/tmp/cxltest4.raw,size=256M
> > > \
> > > -object 
> > > memory-backend-file,id=cxl-lsa1,share=on,mem-path=/tmp/lsa.raw,size=256M
> > > \
> > > -object 
> > > memory-backend-file,id=cxl-lsa2,share=on,mem-path=/tmp/lsa2.raw,size=256M
> > > \
> > > -object 
> > > memory-backend-file,id=cxl-lsa3,share=on,mem-path=/tmp/lsa3.raw,size=256M
> > > \
> > > -object 
> > > memory-backend-file,id=cxl-lsa4,share=on,mem-path=/tmp/lsa4.raw,size=256M
> > > \
> > > -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \
> > > -device pxb-cxl,bus_nr=222,bus=pcie.0,id=cxl.2 \
> > > -device cxl-rp,port=0,bus=cxl.1,id=root_port13,chassis=0,slot=2 \
> > > -device 
> > > cxl-type3,bus=root_port13,memdev=cxl-mem1,lsa=cxl-lsa1,id=cxl-pmem0 \
> > > -device cxl-rp,port=1,bus=cxl.1,id=root_port14,chassis=0,slot=3 \
> > > -device 
> > > cxl-type3,bus=root_port14,memdev=cxl-mem2,lsa=cxl-lsa2,id=cxl-pmem1 \
> > > -device cxl-rp,port=0,bus=cxl.2,id=root_port15,chassis=0,slot=5 \
> > > -device 
> > > cxl-type3,bus=root_port15,memdev=cxl-mem3,lsa=cxl-lsa3,id=cxl-pmem2 \
> > > -device cxl-rp,port=1,bus=cxl.2,id=root_port16,chassis=0,slot=6 \
> > > -device 
> > > cxl-type3,bus=root_port16,memdev=cxl-mem4,lsa=cxl-lsa4,id=cxl-pmem3 \
> > > -M 
> > > cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.targets.1=cxl.2,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k
> > >
> > > Kernel logs show cxl_pci module error while setting up irq
> > > (cxl_event_irqsetup in drivers/cxl/pci.c)
> > >
> > > cxl_pci 0000:0d:00.0: Failed to get interrupt for event Info log
> > > [    3.984800] cxl_pci 0000:e0:00.0: Failed to get interrupt for event 
> > > Info log
> > > [    3.984841] cxl_pci 0000:df:00.0: Failed to get interrupt for event 
> > > Info log
> > >
> > >
> > > Is this expected in an emulated environment?  
> >
> > Upstream QEMU? Or a version of my staging tree?
> >
> > Upstream doesn't support events logs yet, so this may the outcome of that.
> > It missed the 8.0 cycle due to some problems with other series that I'd
> > based it on top of.  Hopefully will start to get those resolved shortly
> > and get as far as events support this cycle.
> >
> > Thanks,
> >
> > Jonathan
> >  
> > >
> > > Regards
> > > Raghu  
> >