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[PATCH 1/3] docs/cxl: fix some typos
From: |
Jonathan Cameron |
Subject: |
[PATCH 1/3] docs/cxl: fix some typos |
Date: |
Fri, 21 Apr 2023 14:45:05 +0100 |
From: Brice Goglin <Brice.Goglin@inria.fr>
Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
docs/system/devices/cxl.rst | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index f25783a4ec..b65480af6f 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -162,7 +162,7 @@ Example system Topology. x marks the match in each decoder
level::
|<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
| __________ __________________________________ __________ |
| | | | | | | |
- | | CFMW 0 | | CXL Fixed Memory Window 1 | | CFMW 1 | |
+ | | CFMW 0 | | CXL Fixed Memory Window 1 | | CFMW 2 | |
| | HB0 only | | Configured to interleave memory | | HB1 only | |
| | | | memory accesses across HB0/HB1 | | | |
| |__________| |_____x____________________________| |__________| |
@@ -208,8 +208,8 @@ Notes:
(1) **3 CXL Fixed Memory Windows (CFMW)** corresponding to different
ranges of the system physical address map. Each CFMW has
particular interleave setup across the CXL Host Bridges (HB)
- CFMW0 provides uninterleaved access to HB0, CFW2 provides
- uninterleaved access to HB1. CFW1 provides interleaved memory access
+ CFMW0 provides uninterleaved access to HB0, CFMW2 provides
+ uninterleaved access to HB1. CFMW1 provides interleaved memory access
across HB0 and HB1.
(2) **Two CXL Host Bridges**. Each of these has 2 CXL Root Ports and
@@ -247,7 +247,7 @@ Example topology involving a switch::
|<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
| __________ __________________________________ __________ |
| | | | | | | |
- | | CFMW 0 | | CXL Fixed Memory Window 1 | | CFMW 1 | |
+ | | CFMW 0 | | CXL Fixed Memory Window 1 | | CFMW 2 | |
| | HB0 only | | Configured to interleave memory | | HB1 only | |
| | | | memory accesses across HB0/HB1 | | | |
| |____x_____| |__________________________________| |__________| |
--
2.37.2