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From: | Richard Henderson |
Subject: | Re: [PATCH v3 5/7] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1 |
Date: | Wed, 19 Apr 2023 07:45:07 +0200 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 |
On 4/19/23 05:27, Weiwei Li wrote:
Fix https://gitlab.com/qemu-project/qemu/-/issues/1542.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1542
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
--- accel/tcg/cputlb.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e984a98dc4..efa0cb67c9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1696,6 +1696,11 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr, if (p == NULL) { return -1; } + + if (full->lg_page_size < TARGET_PAGE_BITS) { + return -1; + } + if (hostp) { *hostp = p; }
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