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Re: [PATCH v2 02/17] target/riscv: Refactor vector-vector translation ma
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v2 02/17] target/riscv: Refactor vector-vector translation macro |
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Date: |
Tue, 18 Apr 2023 12:25:26 +1000 |
On Tue, Apr 18, 2023 at 12:01 AM Lawrence Hunter
<lawrence.hunter@codethink.co.uk> wrote:
>
> From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
>
> Factor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
> function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
> used in proceeding vector-crypto commits.
>
> Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 62 +++++++++++++------------
> 1 file changed, 32 insertions(+), 30 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index f2e3d385152..4106bd69949 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1643,38 +1643,40 @@ GEN_OPIWX_WIDEN_TRANS(vwadd_wx)
> GEN_OPIWX_WIDEN_TRANS(vwsubu_wx)
> GEN_OPIWX_WIDEN_TRANS(vwsub_wx)
>
> +static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
> + gen_helper_gvec_4_ptr *fn, DisasContext *s)
> +{
> + uint32_t data = 0;
> + TCGLabel *over = gen_new_label();
> + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
> +
> + data = FIELD_DP32(data, VDATA, VM, vm);
> + data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> + data = FIELD_DP32(data, VDATA, VTA, s->vta);
> + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
> + data = FIELD_DP32(data, VDATA, VMA, s->vma);
> + tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1),
> + vreg_ofs(s, vs2), cpu_env, s->cfg_ptr->vlen / 8,
> + s->cfg_ptr->vlen / 8, data, fn);
> + mark_vs_dirty(s);
> + gen_set_label(over);
> + return true;
> +}
> +
> /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
> /* OPIVV without GVEC IR */
> -#define GEN_OPIVV_TRANS(NAME, CHECK) \
> -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> -{ \
> - if (CHECK(s, a)) { \
> - uint32_t data = 0; \
> - static gen_helper_gvec_4_ptr * const fns[4] = { \
> - gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
> - gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
> - }; \
> - TCGLabel *over = gen_new_label(); \
> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
> - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
> - \
> - data = FIELD_DP32(data, VDATA, VM, a->vm); \
> - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> - data = FIELD_DP32(data, VDATA, VTA, s->vta); \
> - data = \
> - FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
> - data = FIELD_DP32(data, VDATA, VMA, s->vma); \
> - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> - vreg_ofs(s, a->rs1), \
> - vreg_ofs(s, a->rs2), cpu_env, \
> - s->cfg_ptr->vlen / 8, \
> - s->cfg_ptr->vlen / 8, data, \
> - fns[s->sew]); \
> - mark_vs_dirty(s); \
> - gen_set_label(over); \
> - return true; \
> - } \
> - return false; \
> +#define GEN_OPIVV_TRANS(NAME, CHECK) \
> +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
> +{ \
> + if (CHECK(s, a)) { \
> + static gen_helper_gvec_4_ptr * const fns[4] = { \
> + gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
> + gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
> + }; \
> + return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
> + } \
> + return false; \
> }
>
> /*
> --
> 2.40.0
>
>
- [PATCH v2 00/17] Add RISC-V vector cryptographic instruction set support, Lawrence Hunter, 2023/04/17
- [PATCH v2 05/17] target/riscv: Refactor translation of vector-widening instruction, Lawrence Hunter, 2023/04/17
- [PATCH v2 04/17] target/riscv: Move vector translation checks, Lawrence Hunter, 2023/04/17
- [PATCH v2 08/17] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers, Lawrence Hunter, 2023/04/17
- [PATCH v2 06/17] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/04/17
- [PATCH v2 02/17] target/riscv: Refactor vector-vector translation macro, Lawrence Hunter, 2023/04/17
- [PATCH v2 09/17] target/riscv: Add Zvbb ISA extension support, Lawrence Hunter, 2023/04/17
- [PATCH v2 07/17] qemu/bitops.h: Limit rotate amounts, Lawrence Hunter, 2023/04/17
- [PATCH v2 01/17] target/riscv: Refactor some of the generic vector functionality, Lawrence Hunter, 2023/04/17
- [PATCH v2 03/17] target/riscv: Add Zvbc ISA extension support, Lawrence Hunter, 2023/04/17
- [PATCH v2 14/17] crypto: Create sm4_subword, Lawrence Hunter, 2023/04/17
- [PATCH v2 15/17] crypto: Add SM4 constant parameter CK, Lawrence Hunter, 2023/04/17