Re: [PATCH v2] target/riscv: Restore the predicate() NULL check behavior

[Alistair Francis]

On Mon, Apr 17, 2023 at 2:32 PM Bin Meng <bmeng@tinylab.org> wrote:
>
> When reading a non-existent CSR QEMU should raise illegal instruction
> exception, but currently it just exits due to the g_assert() check.
>
> This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617.
> Some comments are also added to indicate that predicate() must be
> provided for an implemented CSR.
>
> Reported-by: Fei Wu <fei2.wu@intel.com>
> Signed-off-by: Bin Meng <bmeng@tinylab.org>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

>
> ---
>
> Changes in v2:
> - rebase on top of Alistair's riscv-to-apply.next tree
>
>  target/riscv/csr.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index f4d2dcfdc8..7000eb3350 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3817,6 +3817,11 @@ static inline RISCVException 
> riscv_csrrw_check(CPURISCVState *env,
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
>
> +    /* ensure CSR is implemented by checking predicate */
> +    if (!csr_ops[csrno].predicate) {
> +        return RISCV_EXCP_ILLEGAL_INST;
> +    }
> +
>      /* privileged spec version check */
>      if (env->priv_ver < csr_min_priv) {
>          return RISCV_EXCP_ILLEGAL_INST;
> @@ -3834,7 +3839,6 @@ static inline RISCVException 
> riscv_csrrw_check(CPURISCVState *env,
>       * illegal instruction exception should be triggered instead of virtual
>       * instruction exception. Hence this comes after the read / write check.
>       */
> -    g_assert(csr_ops[csrno].predicate != NULL);
>      RISCVException ret = csr_ops[csrno].predicate(env, csrno);
>      if (ret != RISCV_EXCP_NONE) {
>          return ret;
> @@ -4023,7 +4027,10 @@ static RISCVException write_jvt(CPURISCVState *env, 
> int csrno,
>      return RISCV_EXCP_NONE;
>  }
>
> -/* Control and Status Register function table */
> +/*
> + * Control and Status Register function table
> + * riscv_csr_operations::predicate() must be provided for an implemented CSR
> + */
>  riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>      /* User Floating-Point CSRs */
>      [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
> --
> 2.25.1
>
>