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Re: [PATCH] target/i386: Fix exception classes for SSE/AVX instructions.
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH] target/i386: Fix exception classes for SSE/AVX instructions. |
Date: |
Fri, 14 Apr 2023 17:19:18 +0200 |
User-agent: |
Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 |
Hi Ricky,
On 12/2/23 09:28, Ricky Zhou wrote:
Fix the exception classes for some SSE/AVX instructions to match what is
documented in the Intel manual.
Most of these changes have no functional effect on the behavior that
qemu implements (primarily >= 16-byte memory alignment checks). For
example, since qemu does not implement the AC flag, there is no
difference in behavior between Exception Classes 4 and 5 for
instructions where the SSE version only takes <16 byte memory operands.
Having this patch split in 2 (documentation first, logical change then)
would ease code review.
There is one functional change:
Before this change, MOVNTPS and MOVNTPD were labeled as Exception Class
4 (only requiring alignment for legacy SSE instructions). This changes
them to Exception Class 1 (always requiring memory alignment), as
documented in the Intel manual.
This could be a 3rd patch.
Signed-off-by: Ricky Zhou <ricky@rzhou.org>
---
target/i386/tcg/decode-new.c.inc | 79 ++++++++++++++++----------------
1 file changed, 40 insertions(+), 39 deletions(-)
Regards,
Phil.