Re: [RFC PATCH 2/4] target/riscv: Add fcsr field in tb->flags

[Mayuresh Chitale]

On Tue, Apr 11, 2023 at 7:17 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 4/10/23 07:13, Mayuresh Chitale wrote:
> > The state of smstateen0.FCSR bit impacts the execution of floating point
> > instructions when misa.F==0. Add a field in the tb->flags which stores
> > the current state of smstateen0.fcsr and will be used by floating point
> > translation routines.
>
> Are you certain that you require a new bit?
>
> Could the same effect be achieved by forcing one or more of the existing
> TB_FLAGS.{FS,HS_FS} fields to 0 within cpu_get_tb_cpu_state?  I.e. for the 
> purposes of
> translation, pretend the FS state is DISABLED?
Yes, that is correct.
>
> These bits are scarce, are we are nearly out.
>
>
> r~
>