Re: [PATCH v2 28/54] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}

[Daniel Henrique Barboza]

On 4/10/23 22:04, Richard Henderson wrote:
> Interpret the variable argument placement in the caller.
> Mark the argument registers const, because they must be passed to
> add_qemu_ldst_label unmodified.
>
> Pass data_type instead of is64 -- there are several places where
> we already convert back from bool to type.  Clean things up by
> using type throughout.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   tcg/riscv/tcg-target.c.inc | 68 +++++++++++++++-----------------------
>   1 file changed, 26 insertions(+), 42 deletions(-)
>
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 1edc3b1c4d..d4134bc86f 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -1101,7 +1101,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, 
> TCGLabelQemuLdst *l)
>   #endif /* CONFIG_SOFTMMU */
>   
>   static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val,
> -                                   TCGReg base, MemOp opc, bool is_64)
> +                                   TCGReg base, MemOp opc, TCGType type)
>   {
>       /* Byte swapping is left to middle-end expansion. */
>       tcg_debug_assert((opc & MO_BSWAP) == 0);
> @@ -1120,7 +1120,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg 
> val,
>           tcg_out_opc_imm(s, OPC_LH, val, base, 0);
>           break;
>       case MO_UL:
> -        if (is_64) {
> +        if (type == TCG_TYPE_I64) {
>               tcg_out_opc_imm(s, OPC_LWU, val, base, 0);
>               break;
>           }
> @@ -1136,30 +1136,22 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, 
> TCGReg val,
>       }
>   }
>   
> -static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
> +static void tcg_out_qemu_ld(TCGContext *s, const TCGReg data_reg,
> +                            const TCGReg addr_reg, const MemOpIdx oi,
> +                            TCGType data_type)
>   {
> -    TCGReg addr_reg, data_reg;
> -    MemOpIdx oi;
> -    MemOp opc;
> -#if defined(CONFIG_SOFTMMU)
> -    tcg_insn_unit *label_ptr[1];
> -#else
> -    unsigned a_bits;
> -#endif
> +    MemOp opc = get_memop(oi);
>       TCGReg base;
>   
> -    data_reg = *args++;
> -    addr_reg = *args++;
> -    oi = *args++;
> -    opc = get_memop(oi);
> -
>   #if defined(CONFIG_SOFTMMU)
> +    tcg_insn_unit *label_ptr[1];
> +
>       base = tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1);
> -    tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64);
> -    add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
> -                        data_reg, addr_reg, s->code_ptr, label_ptr);
> +    tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type);
> +    add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
> +                        s->code_ptr, label_ptr);
>   #else
> -    a_bits = get_alignment_bits(opc);
> +    unsigned a_bits = get_alignment_bits(opc);
>       if (a_bits) {
>           tcg_out_test_alignment(s, true, addr_reg, a_bits);
>       }
> @@ -1172,7 +1164,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg 
> *args, bool is_64)
>           tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base);
>           base = TCG_REG_TMP0;
>       }
> -    tcg_out_qemu_ld_direct(s, data_reg, base, opc, is_64);
> +    tcg_out_qemu_ld_direct(s, data_reg, base, opc, data_type);
>   #endif
>   }
>   
> @@ -1200,30 +1192,22 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg val,
>       }
>   }
>   
> -static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
> +static void tcg_out_qemu_st(TCGContext *s, const TCGReg data_reg,
> +                            const TCGReg addr_reg, const MemOpIdx oi,
> +                            TCGType data_type)
>   {
> -    TCGReg addr_reg, data_reg;
> -    MemOpIdx oi;
> -    MemOp opc;
> -#if defined(CONFIG_SOFTMMU)
> -    tcg_insn_unit *label_ptr[1];
> -#else
> -    unsigned a_bits;
> -#endif
> +    MemOp opc = get_memop(oi);
>       TCGReg base;
>   
> -    data_reg = *args++;
> -    addr_reg = *args++;
> -    oi = *args++;
> -    opc = get_memop(oi);
> -
>   #if defined(CONFIG_SOFTMMU)
> +    tcg_insn_unit *label_ptr[1];
> +
>       base = tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0);
>       tcg_out_qemu_st_direct(s, data_reg, base, opc);
> -    add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
> -                        data_reg, addr_reg, s->code_ptr, label_ptr);
> +    add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
> +                        s->code_ptr, label_ptr);
>   #else
> -    a_bits = get_alignment_bits(opc);
> +    unsigned a_bits = get_alignment_bits(opc);
>       if (a_bits) {
>           tcg_out_test_alignment(s, false, addr_reg, a_bits);
>       }
> @@ -1528,16 +1512,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
>           break;
>   
>       case INDEX_op_qemu_ld_i32:
> -        tcg_out_qemu_ld(s, args, false);
> +        tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
>           break;
>       case INDEX_op_qemu_ld_i64:
> -        tcg_out_qemu_ld(s, args, true);
> +        tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
>           break;
>       case INDEX_op_qemu_st_i32:
> -        tcg_out_qemu_st(s, args, false);
> +        tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
>           break;
>       case INDEX_op_qemu_st_i64:
> -        tcg_out_qemu_st(s, args, true);
> +        tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
>           break;
>   
>       case INDEX_op_extrh_i64_i32: