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[PATCH v10 00/11] target/arm: Allow CONFIG_TCG=n builds
From: |
Fabiano Rosas |
Subject: |
[PATCH v10 00/11] target/arm: Allow CONFIG_TCG=n builds |
Date: |
Wed, 12 Apr 2023 09:18:18 -0300 |
Rebased on master, moved the neoverse-n1 regs into tcg/cpu64.c and
extracted three new patches from the cpu64 move:
- patch 2: remove dead code from cpu_max_get_sve_max_vq
- patch 3: move TCG -cpu max code into it's own function
- patch 4: add the tcg_enabled || qtest_enabled logic
CI run: https://gitlab.com/farosas/qemu/-/pipelines/834334928
Thanks
v9:
- reverted back to keeping -cpu max code for TCG in tcg/cpu64.c;
- pauth: used tcg_enabled instead of CONFIG_TCG in gdbstub.c. However
we still need to keep the ifdef around the function definition in
gdbstub64.c;
- moved all the regression and test fixes after the patches that
enable the --disable-tcg flag;
- tests with --enable-xen --disable-tcg:
Tests now explicitly skip instead of passing.
We cannot do the check at build time because we build the tests only
once for all the QEMU binaries and the native binary will have
support for KVM, thus breaking our !CONFIG_TCG && !CONFIG_KVM
verification.
I also don't think we can have a wrapper because which accelerators
are used is a test-specific information. The test should be able to
specify which accelerators it needs. In other words there will
always be hardcoded "tcg" and "kvm" strings somewhere.
https://lore.kernel.org/r/20230313151058.19645-1-farosas@suse.de
v8:
https://lore.kernel.org/r/20230309201434.10831-1-farosas@suse.de
v7 resend:
https://lore.kernel.org/r/20230228192628.26140-1-farosas@suse.de
v7:
https://lore.kernel.org/r/20230223130841.25916-1-farosas@suse.de
v6:
https://lore.kernel.org/r/20230217201150.22032-1-farosas@suse.de
v5 resend:
https://lore.kernel.org/r/20230213202927.28992-1-farosas@suse.de
v5:
https://lore.kernel.org/r/20230120184825.31626-1-farosas@suse.de
v4:
https://lore.kernel.org/r/20230119135424.5417-1-farosas@suse.de
v3:
https://lore.kernel.org/r/20230113140419.4013-1-farosas@suse.de
v2:
https://lore.kernel.org/r/20230109224232.11661-1-farosas@suse.de
v1:
https://lore.kernel.org/r/20230104215835.24692-1-farosas@suse.de
Claudio Fontana (1):
target/arm: move cpu_tcg to tcg/cpu32.c
Fabiano Rosas (9):
target/arm: Move cortex sysregs into a separate file
target/arm: Remove dead code from cpu_max_set_sve_max_vq
target/arm: Extract TCG -cpu max code into a function
target/arm: Do not expose all -cpu max features to qtests
target/arm: Move 64-bit TCG CPUs into tcg/
tests/qtest: Fix tests when no KVM or TCG are present
tests/avocado: Pass parameters to migration test
arm/Kconfig: Always select SEMIHOSTING when TCG is present
arm/Kconfig: Do not build TCG-only boards on a KVM-only build
Philippe Mathieu-Daudé (1):
gitlab-ci: Check building KVM-only aarch64 target
.gitlab-ci.d/crossbuilds.yml | 11 +
.../custom-runners/ubuntu-22.04-aarch64.yml | 4 -
configs/devices/aarch64-softmmu/default.mak | 4 -
configs/devices/arm-softmmu/default.mak | 39 -
hw/arm/Kconfig | 43 +-
hw/arm/virt.c | 6 +-
target/arm/Kconfig | 7 +
target/arm/cortex-regs.c | 69 ++
target/arm/cpregs.h | 6 +
target/arm/cpu64.c | 702 +----------------
target/arm/internals.h | 10 +-
target/arm/meson.build | 2 +-
target/arm/{cpu_tcg.c => tcg/cpu32.c} | 72 +-
target/arm/tcg/cpu64.c | 723 ++++++++++++++++++
target/arm/tcg/meson.build | 2 +
tests/avocado/migration.py | 83 +-
tests/qtest/arm-cpu-features.c | 12 +-
tests/qtest/bios-tables-test.c | 11 +-
tests/qtest/boot-serial-test.c | 5 +
tests/qtest/migration-test.c | 9 +-
tests/qtest/pxe-test.c | 8 +-
tests/qtest/vmgenid-test.c | 9 +-
22 files changed, 1007 insertions(+), 830 deletions(-)
create mode 100644 target/arm/cortex-regs.c
rename target/arm/{cpu_tcg.c => tcg/cpu32.c} (93%)
create mode 100644 target/arm/tcg/cpu64.c
--
2.35.3
- [PATCH v10 00/11] target/arm: Allow CONFIG_TCG=n builds,
Fabiano Rosas <=