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[PATCH 0/2] target/riscv: Separate implicitly-enabled and explicitly-ena
From: |
Weiwei Li |
Subject: |
[PATCH 0/2] target/riscv: Separate implicitly-enabled and explicitly-enabled extensions |
Date: |
Mon, 10 Apr 2023 11:35:24 +0800 |
The patch tries to separate the multi-letter extensions that may
implicitly-enabled by misa.EXT from the explicitly-enabled cases, so that the
misa.EXT can truely disabled by write_misa().
With this separation, the implicitly-enabled zve64d/f and zve32f extensions
will no work if we clear misa.V. And clear misa.V will have no effect on the
explicitly-enalbed zve64d/f and zve32f extensions.
Weiwei Li (2):
target/riscv: Add set_implicit_extensions_from_ext() function
target/riscv: Add ext_z*_enabled for implicitly enabled extensions
target/riscv/cpu.c | 73 +++++++++++++++----------
target/riscv/cpu.h | 8 +++
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c | 2 +-
target/riscv/insn_trans/trans_rvd.c.inc | 2 +-
target/riscv/insn_trans/trans_rvf.c.inc | 2 +-
target/riscv/insn_trans/trans_rvi.c.inc | 5 +-
target/riscv/insn_trans/trans_rvv.c.inc | 16 +++---
target/riscv/translate.c | 4 +-
9 files changed, 68 insertions(+), 46 deletions(-)
--
2.25.1
- [PATCH 0/2] target/riscv: Separate implicitly-enabled and explicitly-enabled extensions,
Weiwei Li <=