Re: [PATCH v3 13/20] target/riscv: remove cpu->cfg.ext_u

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:32 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Create a new "u" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are
> replaced with riscv_has_ext(env, RVU).
>
> Remove the old "u" property and 'ext_u' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 9 ++++-----
>  target/riscv/cpu.h | 1 -
>  2 files changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 59f6711f94..a72bc651cf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -400,7 +400,6 @@ static void rv64_thead_c906_cpu_init(Object *obj)
>      set_priv_version(env, PRIV_VERSION_1_11_0);
>
>      cpu->cfg.ext_g = true;
> -    cpu->cfg.ext_u = true;
>      cpu->cfg.ext_icsr = true;
>      cpu->cfg.ext_zfh = true;
>      cpu->cfg.mmu = true;
> @@ -835,7 +834,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>          return;
>      }
>
> -    if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) {
> +    if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
>          error_setg(errp,
>                     "Setting S extension without U extension is illegal");
>          return;
> @@ -1110,7 +1109,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>      if (riscv_has_ext(env, RVS)) {
>          ext |= RVS;
>      }
> -    if (riscv_cpu_cfg(env)->ext_u) {
> +    if (riscv_has_ext(env, RVU)) {
>          ext |= RVU;
>      }
>      if (riscv_cpu_cfg(env)->ext_h) {
> @@ -1448,6 +1447,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>       .misa_bit = RVM, .enabled = true},
>      {.name = "s", .description = "Supervisor-level instructions",
>       .misa_bit = RVS, .enabled = true},
> +    {.name = "u", .description = "User-level instructions",
> +     .misa_bit = RVU, .enabled = true},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1471,7 +1472,6 @@ static void riscv_cpu_add_misa_properties(Object 
> *cpu_obj)
>  static Property riscv_cpu_extensions[] = {
>      /* Defaults for standard extensions */
>      DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
> -    DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>      DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
>      DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
>      DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
> @@ -1578,7 +1578,6 @@ static void register_cpu_props(Object *obj)
>       */
>      if (cpu->env.misa_ext != 0) {
>          cpu->cfg.ext_v = misa_ext & RVV;
> -        cpu->cfg.ext_u = misa_ext & RVU;
>          cpu->cfg.ext_h = misa_ext & RVH;
>          cpu->cfg.ext_j = misa_ext & RVJ;
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index fc35aa7509..7b98cf4dd7 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -419,7 +419,6 @@ typedef struct {
>
>  struct RISCVCPUConfig {
>      bool ext_g;
> -    bool ext_u;
>      bool ext_h;
>      bool ext_j;
>      bool ext_v;
> --
> 2.39.2
>
>