Re: [PATCH v3 10/20] target/riscv: remove cpu->cfg.ext_e

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Create a new "e" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are
> replaced with riscv_has_ext(env, RVE).
>
> Remove the old "e" property and 'ext_e' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 10 +++++-----
>  target/riscv/cpu.h |  1 -
>  2 files changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2156cb380e..9cf3ab3988 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -824,13 +824,13 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>          env->misa_ext_mask = env->misa_ext;
>      }
>
> -    if (riscv_has_ext(env, RVI) && cpu->cfg.ext_e) {
> +    if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
>          error_setg(errp,
>                     "I and E extensions are incompatible");
>          return;
>      }
>
> -    if (!riscv_has_ext(env, RVI) && !cpu->cfg.ext_e) {
> +    if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
>          error_setg(errp,
>                     "Either I or E extension must be set");
>          return;
> @@ -1090,7 +1090,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>      if (riscv_has_ext(env, RVI)) {
>          ext |= RVI;
>      }
> -    if (riscv_cpu_cfg(env)->ext_e) {
> +    if (riscv_has_ext(env, RVE)) {
>          ext |= RVE;
>      }
>      if (riscv_cpu_cfg(env)->ext_m) {
> @@ -1443,6 +1443,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>       .misa_bit = RVF, .enabled = true},
>      {.name = "i", .description = "Base integer instruction set",
>       .misa_bit = RVI, .enabled = true},
> +    {.name = "e", .description = "Base integer instruction set (embedded)",
> +     .misa_bit = RVE, .enabled = false},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1465,7 +1467,6 @@ static void riscv_cpu_add_misa_properties(Object 
> *cpu_obj)
>
>  static Property riscv_cpu_extensions[] = {
>      /* Defaults for standard extensions */
> -    DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
>      DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
>      DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
>      DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
> @@ -1575,7 +1576,6 @@ static void register_cpu_props(Object *obj)
>       * later on.
>       */
>      if (cpu->env.misa_ext != 0) {
> -        cpu->cfg.ext_e = misa_ext & RVE;
>          cpu->cfg.ext_m = misa_ext & RVM;
>          cpu->cfg.ext_v = misa_ext & RVV;
>          cpu->cfg.ext_s = misa_ext & RVS;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 573bf85ff1..cc0b9e73ac 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -418,7 +418,6 @@ typedef struct {
>  } RISCVSATPMap;
>
>  struct RISCVCPUConfig {
> -    bool ext_e;
>      bool ext_g;
>      bool ext_m;
>      bool ext_s;
> --
> 2.39.2
>
>