Re: [PATCH v3 08/20] target/riscv: remove cpu->cfg.ext_f

[Alistair Francis]

On Thu, Mar 30, 2023 at 3:30 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> Create a new "f" RISCVCPUMisaExtConfig property that will update
> env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are
> replaced with riscv_has_ext(env, RVF).
>
> Remove the old "f" property and 'ext_f' from RISCVCPUConfig.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 20 ++++++++++----------
>  target/riscv/cpu.h |  1 -
>  2 files changed, 10 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9bb714d0d8..f53400d40f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -812,12 +812,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>      /* Do some ISA extension error checking */
>      if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
>                              riscv_has_ext(env, RVA) &&
> -                            cpu->cfg.ext_f && riscv_has_ext(env, RVD) &&
> +                            riscv_has_ext(env, RVF) &&
> +                            riscv_has_ext(env, RVD) &&
>                              cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
>          warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
>          cpu->cfg.ext_i = true;
>          cpu->cfg.ext_m = true;
> -        cpu->cfg.ext_f = true;
>          cpu->cfg.ext_icsr = true;
>          cpu->cfg.ext_ifencei = true;
>
> @@ -854,7 +854,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>          return;
>      }
>
> -    if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
> +    if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
>          error_setg(errp, "F extension requires Zicsr");
>          return;
>      }
> @@ -868,12 +868,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>          cpu->cfg.ext_zfhmin = true;
>      }
>
> -    if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) {
> +    if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
>          error_setg(errp, "Zfh/Zfhmin extensions require F extension");
>          return;
>      }
>
> -    if (riscv_has_ext(env, RVD) && !cpu->cfg.ext_f) {
> +    if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
>          error_setg(errp, "D extension requires F extension");
>          return;
>      }
> @@ -898,7 +898,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>          return;
>      }
>
> -    if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) {
> +    if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
>          error_setg(errp, "Zve32f/Zve64f extensions require F extension");
>          return;
>      }
> @@ -931,7 +931,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>              error_setg(errp, "Zfinx extension requires Zicsr");
>              return;
>          }
> -        if (cpu->cfg.ext_f) {
> +        if (riscv_has_ext(env, RVF)) {
>              error_setg(errp,
>                         "Zfinx cannot be supported together with F 
> extension");
>              return;
> @@ -1100,7 +1100,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
>      if (riscv_has_ext(env, RVA)) {
>          ext |= RVA;
>      }
> -    if (riscv_cpu_cfg(env)->ext_f) {
> +    if (riscv_has_ext(env, RVF)) {
>          ext |= RVF;
>      }
>      if (riscv_has_ext(env, RVD)) {
> @@ -1440,6 +1440,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
>       .misa_bit = RVC, .enabled = true},
>      {.name = "d", .description = "Double-precision float point",
>       .misa_bit = RVD, .enabled = true},
> +    {.name = "f", .description = "Single-precision float point",
> +     .misa_bit = RVF, .enabled = true},
>  };
>
>  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
> @@ -1466,7 +1468,6 @@ static Property riscv_cpu_extensions[] = {
>      DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
>      DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
>      DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
> -    DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
>      DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>      DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
> @@ -1577,7 +1578,6 @@ static void register_cpu_props(Object *obj)
>          cpu->cfg.ext_i = misa_ext & RVI;
>          cpu->cfg.ext_e = misa_ext & RVE;
>          cpu->cfg.ext_m = misa_ext & RVM;
> -        cpu->cfg.ext_f = misa_ext & RVF;
>          cpu->cfg.ext_v = misa_ext & RVV;
>          cpu->cfg.ext_s = misa_ext & RVS;
>          cpu->cfg.ext_u = misa_ext & RVU;
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index e4cf79e36f..ce23b1c431 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -422,7 +422,6 @@ struct RISCVCPUConfig {
>      bool ext_e;
>      bool ext_g;
>      bool ext_m;
> -    bool ext_f;
>      bool ext_s;
>      bool ext_u;
>      bool ext_h;
> --
> 2.39.2
>
>