Re: [PATCH v12 10/10] target/riscv: Add support for Zce

[Alistair Francis]

On Tue, Mar 7, 2023 at 6:16 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Add and expose property for Zce:
> * Specifying Zce without F includes Zca, Zcb, Zcmp, Zcmt.
> * Specifying Zce with F includes Zca, Zcb, Zcmp, Zcmt and Zcf.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 12 ++++++++++++
>  target/riscv/cpu.h |  1 +
>  2 files changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d17ae942bd..3502d1e749 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -91,6 +91,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
>      ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb),
>      ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf),
>      ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd),
> +    ISA_EXT_DATA_ENTRY(zce, true, PRIV_VERSION_1_12_0, ext_zce),
>      ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp),
>      ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt),
>      ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
> @@ -945,6 +946,16 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU 
> *cpu, Error **errp)
>          }
>      }
>
> +    if (cpu->cfg.ext_zce) {
> +        cpu->cfg.ext_zca = true;
> +        cpu->cfg.ext_zcb = true;
> +        cpu->cfg.ext_zcmp = true;
> +        cpu->cfg.ext_zcmt = true;
> +        if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
> +            cpu->cfg.ext_zcf = true;
> +        }
> +    }
> +
>      if (cpu->cfg.ext_c) {
>          cpu->cfg.ext_zca = true;
>          if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
> @@ -1501,6 +1512,7 @@ static Property riscv_cpu_extensions[] = {
>      DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
>      DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
>      DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false),
> +    DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false),
>      DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false),
>      DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false),
>      DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 351d5e3e79..9b76885166 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -443,6 +443,7 @@ struct RISCVCPUConfig {
>      bool ext_zca;
>      bool ext_zcb;
>      bool ext_zcd;
> +    bool ext_zce;
>      bool ext_zcf;
>      bool ext_zcmp;
>      bool ext_zcmt;
> --
> 2.25.1
>
>