Re: [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs,vs} from tb

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Re: [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs,vs} from tb_fla

From:	LIU Zhiwei
Subject:	Re: [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs,vs} from tb_flags
Date:	Tue, 28 Mar 2023 10:34:29 +0800
User-agent:	Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0


On 2023/3/25 18:54, Richard Henderson wrote:

Merge with mstatus_{fs,vs}.  We might perform a redundant
assignment to one or the other field, but it's a trivial
and saves 4 bits from TB_FLAGS.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>

Zhiwei

---
  target/riscv/cpu.h        | 16 +++++++---------
  target/riscv/cpu_helper.c | 34 ++++++++++++++++------------------
  target/riscv/translate.c  | 32 ++++++++++----------------------
  3 files changed, 33 insertions(+), 49 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index f787145a21..d9e0eaaf9b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -646,19 +646,17 @@ FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1)
  FIELD(TB_FLAGS, VILL, 14, 1)
  /* Is a Hypervisor instruction load/store allowed? */
  FIELD(TB_FLAGS, HLSX, 15, 1)
-FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
-FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
  /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
-FIELD(TB_FLAGS, XL, 20, 2)
+FIELD(TB_FLAGS, XL, 16, 2)
  /* If PointerMasking should be applied */
-FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1)
-FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1)
-FIELD(TB_FLAGS, VTA, 24, 1)
-FIELD(TB_FLAGS, VMA, 25, 1)
+FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1)
+FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1)
+FIELD(TB_FLAGS, VTA, 20, 1)
+FIELD(TB_FLAGS, VMA, 21, 1)
  /* Native debug itrigger */
-FIELD(TB_FLAGS, ITRIGGER, 26, 1)
+FIELD(TB_FLAGS, ITRIGGER, 22, 1)
  /* Virtual mode enabled */
-FIELD(TB_FLAGS, VIRT_ENABLED, 27, 1)
+FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)

#ifdef TARGET_RISCV32

  #define riscv_cpu_mxl(env)  ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 1e7ee9aa30..4fdd6fe021 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -45,7 +45,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong 
*pc,
  {
      CPUState *cs = env_cpu(env);
      RISCVCPU *cpu = RISCV_CPU(cs);
-
+    RISCVExtStatus fs, vs;
      uint32_t flags = 0;

*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;

@@ -79,18 +79,12 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong 
*pc,
      }

#ifdef CONFIG_USER_ONLY

-    flags = FIELD_DP32(flags, TB_FLAGS, FS, EXT_STATUS_DIRTY);
-    flags = FIELD_DP32(flags, TB_FLAGS, VS, EXT_STATUS_DIRTY);
+    fs = EXT_STATUS_DIRTY;
+    vs = EXT_STATUS_DIRTY;
  #else
      flags |= cpu_mmu_index(env, 0);
-    if (riscv_cpu_fp_enabled(env)) {
-        flags =  FIELD_DP32(flags, TB_FLAGS, FS,
-                            get_field(env->mstatus,  MSTATUS_FS));
-    }
-    if (riscv_cpu_vector_enabled(env)) {
-        flags =  FIELD_DP32(flags, TB_FLAGS, VS,
-                            get_field(env->mstatus, MSTATUS_VS));
-    }
+    fs = get_field(env->mstatus, MSTATUS_FS);
+    vs = get_field(env->mstatus, MSTATUS_VS);

if (riscv_has_ext(env, RVH)) {

          if (env->priv == PRV_M ||
@@ -100,19 +94,23 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong 
*pc,
              flags = FIELD_DP32(flags, TB_FLAGS, HLSX, 1);
          }

- flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_FS,

-                           get_field(env->mstatus_hs, MSTATUS_FS));
-
-        flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
-                           get_field(env->mstatus_hs, MSTATUS_VS));
-        flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED,
-                           get_field(env->virt, VIRT_ONOFF));
+        if (riscv_cpu_virt_enabled(env)) {
+            flags = FIELD_DP32(flags, TB_FLAGS, VIRT_ENABLED, 1);
+            /*
+             * Merge DISABLED and !DIRTY states using MIN.
+             * We will set both fields when dirtying.
+             */
+            fs = MIN(fs, get_field(env->mstatus_hs, MSTATUS_FS));
+            vs = MIN(vs, get_field(env->mstatus_hs, MSTATUS_VS));
+        }
      }
      if (cpu->cfg.debug && !icount_enabled()) {
          flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
      }
  #endif

+ flags = FIELD_DP32(flags, TB_FLAGS, FS, fs);

+    flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
      flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
      if (env->cur_pmmask < (env->xl == MXL_RV32 ? UINT32_MAX : UINT64_MAX)) {
          flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b897bf6006..74d0b9889d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -66,8 +66,6 @@ typedef struct DisasContext {
      uint32_t opcode;
      RISCVExtStatus mstatus_fs;
      RISCVExtStatus mstatus_vs;
-    RISCVExtStatus mstatus_hs_fs;
-    RISCVExtStatus mstatus_hs_vs;
      uint32_t mem_idx;
      /* Remember the rounding mode encoded in the previous fp instruction,
         which we have already installed into env->fp_status.  Or -1 for
@@ -618,16 +616,12 @@ static void mark_fs_dirty(DisasContext *ctx)
          tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
          tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
          tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
-    }

- if (ctx->virt_enabled && ctx->mstatus_hs_fs != EXT_STATUS_DIRTY) {

-        /* Remember the stage change for the rest of the TB. */
-        ctx->mstatus_hs_fs = EXT_STATUS_DIRTY;
-
-        tmp = tcg_temp_new();
-        tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
-        tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
-        tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+        if (ctx->virt_enabled) {
+            tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+            tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
+            tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+        }
      }
  }
  #else
@@ -651,16 +645,12 @@ static void mark_vs_dirty(DisasContext *ctx)
          tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
          tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
          tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
-    }

- if (ctx->virt_enabled && ctx->mstatus_hs_vs != EXT_STATUS_DIRTY) {

-        /* Remember the stage change for the rest of the TB. */
-        ctx->mstatus_hs_vs = EXT_STATUS_DIRTY;
-
-        tmp = tcg_temp_new();
-        tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
-        tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
-        tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+        if (ctx->virt_enabled) {
+            tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+            tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
+            tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
+        }
      }
  }
  #else
@@ -1158,8 +1148,6 @@ static void riscv_tr_init_disas_context(DisasContextBase 
*dcbase, CPUState *cs)
      ctx->misa_ext = env->misa_ext;
      ctx->frm = -1;  /* unknown rounding mode */
      ctx->cfg_ptr = &(cpu->cfg);
-    ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
-    ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS);
      ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
      ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
      ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);

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[PATCH v6 02/25] target/riscv: Add a general status enum for extensions, (continued)
- [PATCH v6 02/25] target/riscv: Add a general status enum for extensions, Richard Henderson, 2023/03/25
  - Re: [PATCH v6 02/25] target/riscv: Add a general status enum for extensions, liweiwei, 2023/03/26
- [PATCH v6 03/25] target/riscv: Encode the FS and VS on a normal way for tb flags, Richard Henderson, 2023/03/25
- [PATCH v6 06/25] target/riscv: Separate priv from mmu_idx, Richard Henderson, 2023/03/25
  - Re: [PATCH v6 06/25] target/riscv: Separate priv from mmu_idx, LIU Zhiwei, 2023/03/27
- [PATCH v6 18/25] target/riscv: Hoist second stage mode change to callers, Richard Henderson, 2023/03/25
- [PATCH v6 23/25] target/riscv: Merge checks for reserved pte flags, Richard Henderson, 2023/03/25
- [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags, Richard Henderson, 2023/03/25
  - Re: [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags, liweiwei, 2023/03/26
    - Re: [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags, Richard Henderson, 2023/03/27
  - Re: [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs,vs} from tb_flags, LIU Zhiwei <=
- [PATCH v6 17/25] target/riscv: Check SUM in the correct register, Richard Henderson, 2023/03/25
- [PATCH v6 21/25] target/riscv: Suppress pte update with is_debug, Richard Henderson, 2023/03/25
- [PATCH v6 25/25] target/riscv: Reorg sum check in get_physical_address, Richard Henderson, 2023/03/25
- [PATCH v6 20/25] target/riscv: Move leaf pte processing out of level loop, Richard Henderson, 2023/03/25
- Re: [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups, Richard Henderson, 2023/03/26
- Re: [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups, liweiwei, 2023/03/26
- Re: [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups, Daniel Henrique Barboza, 2023/03/27
  - Re: [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups, Wu, Fei, 2023/03/27

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