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[PATCH v2 15/19] target/riscv: remove cpu->cfg.ext_v
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v2 15/19] target/riscv: remove cpu->cfg.ext_v |
Date: |
Mon, 27 Mar 2023 19:49:30 -0300 |
Create a new "v" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are
replaced with riscv_has_ext(env, RVV).
Remove the old "v" property and 'ext_v' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 12 +++++-------
target/riscv/cpu.h | 1 -
2 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e02d6f06e8..a916252077 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -877,7 +877,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
}
/* The V vector extension depends on the Zve64d extension */
- if (cpu->cfg.ext_v) {
+ if (riscv_has_ext(env, RVV)) {
cpu->cfg.ext_zve64d = true;
}
@@ -959,7 +959,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
cpu->cfg.ext_zksh = true;
}
- if (cpu->cfg.ext_v) {
+ if (riscv_has_ext(env, RVV)) {
int vext_version = VEXT_VERSION_1_00_0;
if (!is_power_of_2(cpu->cfg.vlen)) {
error_setg(errp,
@@ -1116,7 +1116,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_has_ext(env, RVH)) {
ext |= RVH;
}
- if (riscv_cpu_cfg(env)->ext_v) {
+ if (riscv_has_ext(env, RVV)) {
ext |= RVV;
}
if (riscv_has_ext(env, RVJ)) {
@@ -1454,6 +1454,8 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
.misa_bit = RVH, .enabled = true},
{.name = "x-j", .description = "Dynamic translated languages",
.misa_bit = RVJ, .enabled = false},
+ {.name = "v", .description = "Vector operations",
+ .misa_bit = RVV, .enabled = false},
};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
@@ -1477,7 +1479,6 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
static Property riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
- DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
@@ -1570,7 +1571,6 @@ static Property riscv_cpu_extensions[] = {
static void register_cpu_props(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
- uint32_t misa_ext = cpu->env.misa_ext;
Property *prop;
DeviceState *dev = DEVICE(obj);
@@ -1580,8 +1580,6 @@ static void register_cpu_props(Object *obj)
* later on.
*/
if (cpu->env.misa_ext != 0) {
- cpu->cfg.ext_v = misa_ext & RVV;
-
/*
* We don't want to set the default riscv_cpu_extensions
* in this case.
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 43a40ba950..c0280ace2a 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -419,7 +419,6 @@ typedef struct {
struct RISCVCPUConfig {
bool ext_g;
- bool ext_v;
bool ext_zba;
bool ext_zbb;
bool ext_zbc;
--
2.39.2
- [PATCH v2 05/19] target/riscv: remove cpu->cfg.ext_c, (continued)
- [PATCH v2 05/19] target/riscv: remove cpu->cfg.ext_c, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 08/19] target/riscv: remove cpu->cfg.ext_i, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 09/19] target/riscv: remove cpu->cfg.ext_e, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 10/19] target/riscv: remove cpu->cfg.ext_m, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 12/19] target/riscv: remove cpu->cfg.ext_u, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 13/19] target/riscv: remove cpu->cfg.ext_h, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 14/19] target/riscv: remove cpu->cfg.ext_j, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 07/19] target/riscv: remove cpu->cfg.ext_f, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 04/19] target/riscv: remove cpu->cfg.ext_a, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 11/19] target/riscv: remove cpu->cfg.ext_s, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 15/19] target/riscv: remove cpu->cfg.ext_v,
Daniel Henrique Barboza <=
- [PATCH v2 16/19] target/riscv: remove riscv_cpu_sync_misa_cfg(), Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 17/19] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init(), Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 18/19] target/riscv: add RVG and remove cpu->cfg.ext_g, Daniel Henrique Barboza, 2023/03/27
- [PATCH v2 19/19] target/riscv/cpu.c: redesign register_cpu_props(), Daniel Henrique Barboza, 2023/03/27