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[PATCH v6 25/25] target/riscv: Reorg sum check in get_physical_address
From: |
Richard Henderson |
Subject: |
[PATCH v6 25/25] target/riscv: Reorg sum check in get_physical_address |
Date: |
Sat, 25 Mar 2023 03:54:29 -0700 |
Implement this by adjusting prot, which reduces the set of
checks required. This prevents exec to be set for U pages
in MMUIdx_S_SUM. While it had been technically incorrect,
it did not manifest as a bug, because we will never attempt
to execute from MMUIdx_S_SUM.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_helper.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 725ca45106..7336d1273b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -800,7 +800,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
*ret_prot = 0;
hwaddr base;
- int levels, ptidxbits, ptesize, vm, sum, widened;
+ int levels, ptidxbits, ptesize, vm, widened;
if (first_stage == true) {
if (use_background) {
@@ -831,7 +831,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
}
widened = 2;
}
- sum = mmuidx_sum(mmu_idx);
+
switch (vm) {
case VM_1_10_SV32:
levels = 2; ptidxbits = 10; ptesize = 4; break;
@@ -999,15 +999,15 @@ restart:
prot |= PAGE_EXEC;
}
- if ((pte & PTE_U) &&
- ((mode != PRV_U) && (!sum || access_type == MMU_INST_FETCH))) {
- /*
- * User PTE flags when not U mode and mstatus.SUM is not set,
- * or the access type is an instruction fetch.
- */
- return TRANSLATE_FAIL;
- }
- if (!(pte & PTE_U) && (mode != PRV_S)) {
+ if (pte & PTE_U) {
+ if (mode != PRV_U) {
+ if (!mmuidx_sum(mmu_idx)) {
+ return TRANSLATE_FAIL;
+ }
+ /* SUM allows only read+write, not execute. */
+ prot &= PAGE_READ | PAGE_WRITE;
+ }
+ } else if (mode != PRV_S) {
/* Supervisor PTE flags when not S mode */
return TRANSLATE_FAIL;
}
--
2.34.1
- Re: [PATCH v6 02/25] target/riscv: Add a general status enum for extensions, (continued)
- [PATCH v6 03/25] target/riscv: Encode the FS and VS on a normal way for tb flags, Richard Henderson, 2023/03/25
- [PATCH v6 06/25] target/riscv: Separate priv from mmu_idx, Richard Henderson, 2023/03/25
- [PATCH v6 18/25] target/riscv: Hoist second stage mode change to callers, Richard Henderson, 2023/03/25
- [PATCH v6 23/25] target/riscv: Merge checks for reserved pte flags, Richard Henderson, 2023/03/25
- [PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags, Richard Henderson, 2023/03/25
- [PATCH v6 17/25] target/riscv: Check SUM in the correct register, Richard Henderson, 2023/03/25
- [PATCH v6 21/25] target/riscv: Suppress pte update with is_debug, Richard Henderson, 2023/03/25
- [PATCH v6 25/25] target/riscv: Reorg sum check in get_physical_address,
Richard Henderson <=
- [PATCH v6 20/25] target/riscv: Move leaf pte processing out of level loop, Richard Henderson, 2023/03/25
- Re: [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups, Richard Henderson, 2023/03/26
- Re: [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups, liweiwei, 2023/03/26
- Re: [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups, Daniel Henrique Barboza, 2023/03/27