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[PATCH v6 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX
From: |
Richard Henderson |
Subject: |
[PATCH v6 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX |
Date: |
Sat, 25 Mar 2023 03:54:13 -0700 |
Use the new functions to properly check execute permission
for the read rather than read permission.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/op_helper.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 962a061228..b2169a99ff 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -427,18 +427,27 @@ void helper_hyp_gvma_tlb_flush(CPURISCVState *env)
helper_hyp_tlb_flush(env);
}
+/*
+ * TODO: These implementations are not quite correct. They perform the
+ * access using execute permission just fine, but the final PMP check
+ * is supposed to have read permission as well. Without replicating
+ * a fair fraction of cputlb.c, fixing this requires adding new mmu_idx
+ * which would imply that exact check in tlb_fill.
+ */
target_ulong helper_hyp_hlvx_hu(CPURISCVState *env, target_ulong address)
{
int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
+ MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx);
- return cpu_lduw_mmuidx_ra(env, address, mmu_idx, GETPC());
+ return cpu_ldw_code_mmu(env, address, oi, GETPC());
}
target_ulong helper_hyp_hlvx_wu(CPURISCVState *env, target_ulong address)
{
int mmu_idx = cpu_mmu_index(env, true) | MMU_HYP_ACCESS_BIT;
+ MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx);
- return cpu_ldl_mmuidx_ra(env, address, mmu_idx, GETPC());
+ return cpu_ldl_code_mmu(env, address, oi, GETPC());
}
#endif /* !CONFIG_USER_ONLY */
--
2.34.1
[PATCH v6 10/25] target/riscv: Handle HLV, HSV via helpers, Richard Henderson, 2023/03/25
[PATCH v6 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX,
Richard Henderson <=
[PATCH v6 14/25] target/riscv: Introduce mmuidx_2stage, Richard Henderson, 2023/03/25
[PATCH v6 22/25] target/riscv: Don't modify SUM with is_debug, Richard Henderson, 2023/03/25
[PATCH v6 19/25] target/riscv: Hoist pbmte and hade out of the level loop, Richard Henderson, 2023/03/25
[PATCH v6 12/25] target/riscv: Introduce mmuidx_sum, Richard Henderson, 2023/03/25
[PATCH v6 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT, Richard Henderson, 2023/03/25
[PATCH v6 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change, Richard Henderson, 2023/03/25
[PATCH v6 15/25] target/riscv: Move hstatus.spvp check to check_access_hlsv, Richard Henderson, 2023/03/25
[PATCH v6 01/25] target/riscv: Extract virt enabled state from tb flags, Richard Henderson, 2023/03/25
[PATCH v6 16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index, Richard Henderson, 2023/03/25