Re: [PATCH qemu v3] linux-user: Emulate /proc/cpuinfo output for riscv

[Laurent Vivier]

Le 23/03/2023 à 08:52, Laurent Vivier a écrit :
> Le 21/03/2023 à 19:25, Afonso Bordado a écrit :
> > RISC-V does not expose all extensions via hwcaps, thus some userspace
> > applications may want to query these via /proc/cpuinfo.
> >
> > Currently when querying this file the host's file is shown instead
> > which is slightly confusing. Emulate a basic /proc/cpuinfo file
> > with mmu info and an ISA string.
> >
> > Signed-off-by: Afonso Bordado <afonsobordado@gmail.com>
> > Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
> > Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> > Reviewed-by: Laurent Vivier <laurent@vivier.eu>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> > ---
> >
> > Thanks everyone for reviewing! Should I resend this once the 8.0
> > freeze is over? Or does someone queue it for inclusion in the next
> > version?
>
> I queue this for 8.1 in the linux-use branch.

I've applied v2 as v3 seems to be corrupted. I've removed the changelog from 
the commit message.

Thanks,
Laurent

> Thanks,
> Laurent
> > Changes from V2:
> > - Update ChangeLog Location
> >
> > Changes from V1:
> > - Call `g_free` on ISA string.
> > - Use `riscv_cpu_cfg` API.
> > - Query `cpu_env->xl` to check for RV32.
> >
> >
> >   linux-user/syscall.c              | 34 +++++++++++++++++++++++++++++--
> >   tests/tcg/riscv64/Makefile.target |  1 +
> >   tests/tcg/riscv64/cpuinfo.c       | 30 +++++++++++++++++++++++++++
> >   3 files changed, 63 insertions(+), 2 deletions(-)
> >   create mode 100644 tests/tcg/riscv64/cpuinfo.c
> >
> > diff --git a/linux-user/syscall.c b/linux-user/syscall.c
> > index 24cea6fb6a..0388f8b0b0 100644
> > --- a/linux-user/syscall.c
> > +++ b/linux-user/syscall.c
> > @@ -8230,7 +8230,8 @@ void target_exception_dump(CPUArchState *env, const char 
> > *fmt, int code)
> >   }
> >
> >   #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \
> > -    defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA)
> > +    defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) || \
> > +    defined(TARGET_RISCV)
> >   static int is_proc(const char *filename, const char *entry)
> >   {
> >       return strcmp(filename, entry) == 0;
> > @@ -8308,6 +8309,35 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd)
> >   }
> >   #endif
> >
> > +#if defined(TARGET_RISCV)
> > +static int open_cpuinfo(CPUArchState *cpu_env, int fd)
> > +{
> > +    int i;
> > +    int num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
> > +    RISCVCPU *cpu = env_archcpu(cpu_env);
> > +    const RISCVCPUConfig *cfg = riscv_cpu_cfg((CPURISCVState *) cpu_env);
> > +    char *isa_string = riscv_isa_string(cpu);
> > +    const char *mmu;
> > +
> > +    if (cfg->mmu) {
> > +        mmu = (cpu_env->xl == MXL_RV32) ? "sv32"  : "sv48";
> > +    } else {
> > +        mmu = "none";
> > +    }
> > +
> > +    for (i = 0; i < num_cpus; i++) {
> > +        dprintf(fd, "processor\t: %d\n", i);
> > +        dprintf(fd, "hart\t\t: %d\n", i);
> > +        dprintf(fd, "isa\t\t: %s\n", isa_string);
> > +        dprintf(fd, "mmu\t\t: %s\n", mmu);
> > +        dprintf(fd, "uarch\t\t: qemu\n\n");
> > +    }
> > +
> > +    g_free(isa_string);
> > +    return 0;
> > +}
> > +#endif
> > +
> >   #if defined(TARGET_M68K)
> >   static int open_hardware(CPUArchState *cpu_env, int fd)
> >   {
> > @@ -8332,7 +8362,7 @@ static int do_openat(CPUArchState *cpu_env, int dirfd, const char *pathname, 
> > int
> >   #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
> >           { "/proc/net/route", open_net_route, is_proc },
> >   #endif
> > -#if defined(TARGET_SPARC) || defined(TARGET_HPPA)
> > +#if defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined(TARGET_RISCV)
> >           { "/proc/cpuinfo", open_cpuinfo, is_proc },
> >   #endif
> >   #if defined(TARGET_M68K)
> > diff --git a/tests/tcg/riscv64/Makefile.target
> > b/tests/tcg/riscv64/Makefile.target
> > index cc3ed65ffd..df93a2ce1f 100644
> > --- a/tests/tcg/riscv64/Makefile.target
> > +++ b/tests/tcg/riscv64/Makefile.target
> > @@ -4,6 +4,7 @@
> >   VPATH += $(SRC_PATH)/tests/tcg/riscv64
> >   TESTS += test-div
> >   TESTS += noexec
> > +TESTS += cpuinfo
> >
> >   # Disable compressed instructions for test-noc
> >   TESTS += test-noc
> > diff --git a/tests/tcg/riscv64/cpuinfo.c b/tests/tcg/riscv64/cpuinfo.c
> > new file mode 100644
> > index 0000000000..296abd0a8c
> > --- /dev/null
> > +++ b/tests/tcg/riscv64/cpuinfo.c
> > @@ -0,0 +1,30 @@
> > +#include <stdio.h>
> > +#include <stdlib.h>
> > +#include <string.h>
> > +#include <assert.h>
> > +
> > +#define BUFFER_SIZE 1024
> > +
> > +int main(void)
> > +{
> > +    char buffer[BUFFER_SIZE];
> > +    FILE *fp = fopen("/proc/cpuinfo", "r");
> > +    assert(fp != NULL);
> > +
> > +    while (fgets(buffer, BUFFER_SIZE, fp) != NULL) {
> > +        if (strstr(buffer, "processor") != NULL) {
> > +            assert(strstr(buffer, "processor\t: ") == buffer);
> > +        } else if (strstr(buffer, "hart") != NULL) {
> > +            assert(strstr(buffer, "hart\t\t: ") == buffer);
> > +        } else if (strstr(buffer, "isa") != NULL) {
> > +            assert(strcmp(buffer, "isa\t\t: rv64imafdc_zicsr_zifencei\n") == 
> > 0);
> > +        } else if (strstr(buffer, "mmu") != NULL) {
> > +            assert(strcmp(buffer, "mmu\t\t: sv48\n") == 0);
> > +        } else if (strstr(buffer, "uarch") != NULL) {
> > +            assert(strcmp(buffer, "uarch\t\t: qemu\n") == 0);
> > +        }
> > +    }
> > +
> > +    fclose(fp);
> > +    return 0;
> > +}