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[PATCH for-8.1 v4 19/25] target/riscv: write env->misa_ext* in register_
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH for-8.1 v4 19/25] target/riscv: write env->misa_ext* in register_generic_cpu_props() |
Date: |
Wed, 22 Mar 2023 19:19:58 -0300 |
In the process of creating the user-facing flags in
register_generic_cpu_props() we're also setting default values for the
cpu->cfg flags that represents MISA bits.
Leaving it as is will cause a discrepancy between users of this function
(at this moment the non-named CPUs) and named CPUs. Named CPUs are using
set_misa() with a non-zero 'ext' value, writing cpu->cfg in the process.
They'll reach riscv_cpu_realize() in a state where env->misa_ext will
reflect cpu->cfg, allowing functions to choose whether to use
env->misa_ext or cpu->cfg to validate MISA bits.
If we guarantee that env->misa_ext will always reflect cpu->cfg at the
start of riscv_cpu_realize(), functions will be able to no longer rely
on cpu->cfg for MISA validation. This happens to be one blocker we have
to properly support write_misa().
Sync env->misa_ext* in register_generic_cpu_props(). After that, there
will be no more places where env->misa_ext needs to be sync back with
cpu->cfg, so remove the now obsolete code at the end of
riscv_cpu_validate_set_extensions().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 22 ++++++++++++----------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d2eb2b3ba1..f1e82a8dda 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1107,14 +1107,10 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu,
Error **errp)
/*
* Check consistency between chosen extensions while setting
- * cpu->cfg accordingly, setting env->misa_ext and
- * misa_ext_mask in the end.
+ * cpu->cfg accordingly.
*/
static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
{
- CPURISCVState *env = &cpu->env;
- uint32_t ext = 0;
-
if (cpu->cfg.epmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available
@@ -1231,10 +1227,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
* validated and set everything we need.
*/
riscv_cpu_disable_priv_spec_isa_exts(cpu);
-
- ext = riscv_get_misa_ext_with_cpucfg(&cpu->cfg);
-
- env->misa_ext_mask = env->misa_ext = ext;
}
#ifndef CONFIG_USER_ONLY
@@ -1345,6 +1337,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+ /*
+ * This is the last point where env->misa_ext* can
+ * be changed.
+ */
if (cpu->cfg.ext_g) {
riscv_cpu_enable_g(cpu, &local_err);
if (local_err != NULL) {
@@ -1622,10 +1618,12 @@ static Property riscv_cpu_extensions[] = {
* Register generic CPU props with user-facing flags declared
* in riscv_cpu_extensions[].
*
- * Note that this will overwrite existing values in cpu->cfg.
+ * Note that this will overwrite existing values in cpu->cfg
+ * and MISA.
*/
static void register_generic_cpu_props(Object *obj)
{
+ RISCVCPU *cpu = RISCV_CPU(obj);
Property *prop;
DeviceState *dev = DEVICE(obj);
@@ -1636,6 +1634,10 @@ static void register_generic_cpu_props(Object *obj)
#ifndef CONFIG_USER_ONLY
riscv_add_satp_mode_properties(obj);
#endif
+
+ /* Keep env->misa_ext and misa_ext_mask updated */
+ cpu->env.misa_ext = riscv_get_misa_ext_with_cpucfg(&cpu->cfg);
+ cpu->env.misa_ext_mask = cpu->env.misa_ext;
}
static Property riscv_cpu_properties[] = {
--
2.39.2
- [PATCH for-8.1 v4 00/25] target/riscv: rework CPU extensions validation, Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 08/25] target/riscv/cpu.c: validate extensions before riscv_timer_init(), Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 07/25] target/riscv: move pmp and epmp validations to validate_set_extensions(), Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 13/25] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers, Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 04/25] target/riscv: add PRIV_VERSION_LATEST, Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 18/25] target/riscv: error out on priv failure for RVH, Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 20/25] target/riscv: make validate_misa_ext() use a misa_ext val, Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 19/25] target/riscv: write env->misa_ext* in register_generic_cpu_props(),
Daniel Henrique Barboza <=
- [PATCH for-8.1 v4 21/25] target/riscv: split riscv_cpu_validate_set_extensions(), Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 22/25] target/riscv: use misa_ext val in riscv_cpu_validate_extensions(), Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 17/25] target/riscv: move riscv_cpu_validate_v() to validate_misa_ext(), Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 10/25] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions(), Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 05/25] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers, Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 14/25] target/riscv: add RVG, Daniel Henrique Barboza, 2023/03/22
- [PATCH for-8.1 v4 23/25] target/riscv: rework write_misa(), Daniel Henrique Barboza, 2023/03/22