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[PATCH v4 09/12] target/s390x: Handle STRL to non-aligned addresses
From: |
Ilya Leoshkevich |
Subject: |
[PATCH v4 09/12] target/s390x: Handle STRL to non-aligned addresses |
Date: |
Thu, 16 Mar 2023 17:44:25 +0100 |
Use MO_ALIGN and let do_unaligned_access() generate a specification
exception.
Reported-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Suggested-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
---
target/s390x/tcg/insn-data.h.inc | 12 ++++++------
target/s390x/tcg/translate.c | 3 ++-
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index 3abd2dbedd5..30c02b3fcd6 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -840,15 +840,15 @@
F(0xed15, SQDB, RXE, Z, 0, m2_64, new, f1, sqdb, 0, IF_BFP)
/* STORE */
- C(0x5000, ST, RX_a, Z, r1_o, a2, 0, 0, st32, 0)
- C(0xe350, STY, RXY_a, LD, r1_o, a2, 0, 0, st32, 0)
+ D(0x5000, ST, RX_a, Z, r1_o, a2, 0, 0, st32, 0, 0)
+ D(0xe350, STY, RXY_a, LD, r1_o, a2, 0, 0, st32, 0, 0)
C(0xe324, STG, RXY_a, Z, r1_o, a2, 0, 0, st64, 0)
F(0x6000, STD, RX_a, Z, f1, a2, 0, 0, st64, 0, IF_AFP1)
F(0xed67, STDY, RXY_a, LD, f1, a2, 0, 0, st64, 0, IF_AFP1)
- F(0x7000, STE, RX_a, Z, e1, a2, 0, 0, st32, 0, IF_AFP1)
- F(0xed66, STEY, RXY_a, LD, e1, a2, 0, 0, st32, 0, IF_AFP1)
+ E(0x7000, STE, RX_a, Z, e1, a2, 0, 0, st32, 0, 0, IF_AFP1)
+ E(0xed66, STEY, RXY_a, LD, e1, a2, 0, 0, st32, 0, 0, IF_AFP1)
/* STORE RELATIVE LONG */
- C(0xc40f, STRL, RIL_b, GIE, r1_o, ri2, 0, 0, st32, 0)
+ D(0xc40f, STRL, RIL_b, GIE, r1_o, ri2, 0, 0, st32, 0, MO_ALIGN)
C(0xc40b, STGRL, RIL_b, GIE, r1_o, ri2, 0, 0, st64, 0)
/* STORE CHARACTER */
C(0x4200, STC, RX_a, Z, r1_o, a2, 0, 0, st8, 0)
@@ -867,7 +867,7 @@
/* STORE HALFWORD RELATIVE LONG */
C(0xc407, STHRL, RIL_b, GIE, r1_o, ri2, 0, 0, st16, 0)
/* STORE HIGH */
- C(0xe3cb, STFH, RXY_a, HW, r1_sr32, a2, 0, 0, st32, 0)
+ D(0xe3cb, STFH, RXY_a, HW, r1_sr32, a2, 0, 0, st32, 0, 0)
/* STORE ON CONDITION */
D(0xebf3, STOC, RSY_b, LOC, 0, 0, 0, 0, soc, 0, 0)
D(0xebe3, STOCG, RSY_b, LOC, 0, 0, 0, 0, soc, 0, 1)
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index c67f8440db8..8fd21425dba 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -4370,7 +4370,8 @@ static DisasJumpType op_st16(DisasContext *s, DisasOps *o)
static DisasJumpType op_st32(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_tl(o->in1, o->in2, get_mem_index(s),
+ MO_TEUL | s->insn->data);
return DISAS_NEXT;
}
--
2.39.2
- [PATCH v4 00/12] target/s390x: Handle unaligned accesses, Ilya Leoshkevich, 2023/03/16
- [PATCH v4 01/12] target/s390x: Handle branching to odd addresses, Ilya Leoshkevich, 2023/03/16
- [PATCH v4 02/12] target/s390x: Handle EXECUTE of odd addresses, Ilya Leoshkevich, 2023/03/16
- [PATCH v4 03/12] target/s390x: Handle LGRL from non-aligned addresses, Ilya Leoshkevich, 2023/03/16
- [PATCH v4 05/12] target/s390x: Handle LLGFRL from non-aligned addresses, Ilya Leoshkevich, 2023/03/16
- [PATCH v4 04/12] target/s390x: Handle LRL and LGFRL from non-aligned addresses, Ilya Leoshkevich, 2023/03/16
- [PATCH v4 07/12] target/s390x: Handle CGRL and CLGRL with non-aligned addresses, Ilya Leoshkevich, 2023/03/16
- [PATCH v4 06/12] target/s390x: Handle CRL and CGFRL with non-aligned addresses, Ilya Leoshkevich, 2023/03/16
- [PATCH v4 08/12] target/s390x: Handle CLRL and CLGFRL with non-aligned addresses, Ilya Leoshkevich, 2023/03/16
- [PATCH v4 09/12] target/s390x: Handle STRL to non-aligned addresses,
Ilya Leoshkevich <=
- [PATCH v4 10/12] target/s390x: Handle STGRL to non-aligned addresses, Ilya Leoshkevich, 2023/03/16
- [PATCH v4 11/12] target/s390x: Update do_unaligned_access() comment, Ilya Leoshkevich, 2023/03/16
- [PATCH v4 12/12] tests/tcg/s390x: Test unaligned accesses, Ilya Leoshkevich, 2023/03/16