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Re: [PATCH v4] target/arm: Add Neoverse-N1 registers
From: |
Peter Maydell |
Subject: |
Re: [PATCH v4] target/arm: Add Neoverse-N1 registers |
Date: |
Mon, 13 Mar 2023 15:17:52 +0000 |
On Mon, 13 Mar 2023 at 03:39, Chen Baozi <chenbaozi@phytium.com.cn> wrote:
>
> Add implementation defined registers for neoverse-n1 which
> would be accessed by TF-A. Since there is no DSU in Qemu,
> CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition.
>
> Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
> ---
> target/arm/cpu64.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 69 insertions(+)
>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM