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[PULL V2 05/44] e1000: Mask registers when writing
From: |
Jason Wang |
Subject: |
[PULL V2 05/44] e1000: Mask registers when writing |
Date: |
Fri, 10 Mar 2023 17:34:47 +0800 |
From: Akihiko Odaki <akihiko.odaki@daynix.com>
When a register has effective bits fewer than their width, the old code
inconsistently masked when writing or reading. Make the code consistent
by always masking when writing, and remove some code duplication.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
---
hw/net/e1000.c | 84 ++++++++++++++++++++++------------------------------------
1 file changed, 31 insertions(+), 53 deletions(-)
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
index 9619a2e..0925a99 100644
--- a/hw/net/e1000.c
+++ b/hw/net/e1000.c
@@ -1063,30 +1063,6 @@ mac_readreg(E1000State *s, int index)
}
static uint32_t
-mac_low4_read(E1000State *s, int index)
-{
- return s->mac_reg[index] & 0xf;
-}
-
-static uint32_t
-mac_low11_read(E1000State *s, int index)
-{
- return s->mac_reg[index] & 0x7ff;
-}
-
-static uint32_t
-mac_low13_read(E1000State *s, int index)
-{
- return s->mac_reg[index] & 0x1fff;
-}
-
-static uint32_t
-mac_low16_read(E1000State *s, int index)
-{
- return s->mac_reg[index] & 0xffff;
-}
-
-static uint32_t
mac_icr_read(E1000State *s, int index)
{
uint32_t ret = s->mac_reg[ICR];
@@ -1138,11 +1114,17 @@ set_rdt(E1000State *s, int index, uint32_t val)
}
}
-static void
-set_16bit(E1000State *s, int index, uint32_t val)
-{
- s->mac_reg[index] = val & 0xffff;
-}
+#define LOW_BITS_SET_FUNC(num) \
+ static void \
+ set_##num##bit(E1000State *s, int index, uint32_t val) \
+ { \
+ s->mac_reg[index] = val & (BIT(num) - 1); \
+ }
+
+LOW_BITS_SET_FUNC(4)
+LOW_BITS_SET_FUNC(11)
+LOW_BITS_SET_FUNC(13)
+LOW_BITS_SET_FUNC(16)
static void
set_dlen(E1000State *s, int index, uint32_t val)
@@ -1196,7 +1178,9 @@ static const readops macreg_readops[] = {
getreg(XONRXC), getreg(XONTXC), getreg(XOFFRXC), getreg(XOFFTXC),
getreg(RFC), getreg(RJC), getreg(RNBC), getreg(TSCTFC),
getreg(MGTPRC), getreg(MGTPDC), getreg(MGTPTC), getreg(GORCL),
- getreg(GOTCL),
+ getreg(GOTCL), getreg(RDFH), getreg(RDFT), getreg(RDFHS),
+ getreg(RDFTS), getreg(RDFPC), getreg(TDFH), getreg(TDFT),
+ getreg(TDFHS), getreg(TDFTS), getreg(TDFPC), getreg(AIT),
[TOTH] = mac_read_clr8, [TORH] = mac_read_clr8,
[GOTCH] = mac_read_clr8, [GORCH] = mac_read_clr8,
@@ -1214,22 +1198,15 @@ static const readops macreg_readops[] = {
[MPTC] = mac_read_clr4,
[ICR] = mac_icr_read, [EECD] = get_eecd,
[EERD] = flash_eerd_read,
- [RDFH] = mac_low13_read, [RDFT] = mac_low13_read,
- [RDFHS] = mac_low13_read, [RDFTS] = mac_low13_read,
- [RDFPC] = mac_low13_read,
- [TDFH] = mac_low11_read, [TDFT] = mac_low11_read,
- [TDFHS] = mac_low13_read, [TDFTS] = mac_low13_read,
- [TDFPC] = mac_low13_read,
- [AIT] = mac_low16_read,
[CRCERRS ... MPC] = &mac_readreg,
[IP6AT ... IP6AT + 3] = &mac_readreg, [IP4AT ... IP4AT + 6] =
&mac_readreg,
- [FFLT ... FFLT + 6] = &mac_low11_read,
+ [FFLT ... FFLT + 6] = &mac_readreg,
[RA ... RA + 31] = &mac_readreg,
[WUPM ... WUPM + 31] = &mac_readreg,
[MTA ... MTA + 127] = &mac_readreg,
[VFTA ... VFTA + 127] = &mac_readreg,
- [FFMT ... FFMT + 254] = &mac_low4_read,
+ [FFMT ... FFMT + 254] = &mac_readreg,
[FFVT ... FFVT + 254] = &mac_readreg,
[PBM ... PBM + 16383] = &mac_readreg,
};
@@ -1241,26 +1218,27 @@ static const writeops macreg_writeops[] = {
putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
putreg(RDBAL), putreg(LEDCTL), putreg(VET), putreg(FCRUC),
- putreg(TDFH), putreg(TDFT), putreg(TDFHS), putreg(TDFTS),
- putreg(TDFPC), putreg(RDFH), putreg(RDFT), putreg(RDFHS),
- putreg(RDFTS), putreg(RDFPC), putreg(IPAV), putreg(WUC),
- putreg(WUS), putreg(AIT),
-
- [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
- [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
- [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
- [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
- [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
- [RDTR] = set_16bit, [RADV] = set_16bit, [TADV] = set_16bit,
- [ITR] = set_16bit,
+ putreg(IPAV), putreg(WUC),
+ putreg(WUS),
+
+ [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
+ [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
+ [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
+ [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
+ [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
+ [RDTR] = set_16bit, [RADV] = set_16bit, [TADV] = set_16bit,
+ [ITR] = set_16bit, [TDFH] = set_11bit, [TDFT] = set_11bit,
+ [TDFHS] = set_13bit, [TDFTS] = set_13bit, [TDFPC] = set_13bit,
+ [RDFH] = set_13bit, [RDFT] = set_13bit, [RDFHS] = set_13bit,
+ [RDFTS] = set_13bit, [RDFPC] = set_13bit, [AIT] = set_16bit,
[IP6AT ... IP6AT + 3] = &mac_writereg, [IP4AT ... IP4AT + 6] =
&mac_writereg,
- [FFLT ... FFLT + 6] = &mac_writereg,
+ [FFLT ... FFLT + 6] = &set_11bit,
[RA ... RA + 31] = &mac_writereg,
[WUPM ... WUPM + 31] = &mac_writereg,
[MTA ... MTA + 127] = &mac_writereg,
[VFTA ... VFTA + 127] = &mac_writereg,
- [FFMT ... FFMT + 254] = &mac_writereg, [FFVT ... FFVT + 254] =
&mac_writereg,
+ [FFMT ... FFMT + 254] = &set_4bit, [FFVT ... FFVT + 254] =
&mac_writereg,
[PBM ... PBM + 16383] = &mac_writereg,
};
--
2.7.4
- [PULL V2 00/44] Net patches, Jason Wang, 2023/03/10
- [PULL V2 01/44] e1000e: Fix the code style, Jason Wang, 2023/03/10
- [PULL V2 02/44] hw/net: Add more MII definitions, Jason Wang, 2023/03/10
- [PULL V2 03/44] fsl_etsec: Use hw/net/mii.h, Jason Wang, 2023/03/10
- [PULL V2 05/44] e1000: Mask registers when writing,
Jason Wang <=
- [PULL V2 04/44] e1000: Use hw/net/mii.h, Jason Wang, 2023/03/10
- [PULL V2 07/44] e1000e: Mask registers when writing, Jason Wang, 2023/03/10
- [PULL V2 06/44] e1000e: Introduce E1000E_LOW_BITS_SET_FUNC, Jason Wang, 2023/03/10
- [PULL V2 08/44] e1000: Use more constant definitions, Jason Wang, 2023/03/10
- [PULL V2 09/44] e1000e: Use more constant definitions, Jason Wang, 2023/03/10
- [PULL V2 10/44] e1000: Use memcpy to intialize registers, Jason Wang, 2023/03/10
- [PULL V2 11/44] e1000e: Use memcpy to intialize registers, Jason Wang, 2023/03/10
- [PULL V2 12/44] e1000e: Remove pending interrupt flags, Jason Wang, 2023/03/10
- [PULL V2 13/44] e1000e: Improve software reset, Jason Wang, 2023/03/10
- [PULL V2 14/44] e1000: Configure ResettableClass, Jason Wang, 2023/03/10