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[PATCH 24/45] target/riscv: Add vaesem.vv decoding, translation and exec
From: |
Lawrence Hunter |
Subject: |
[PATCH 24/45] target/riscv: Add vaesem.vv decoding, translation and execution support |
Date: |
Fri, 10 Mar 2023 09:11:54 +0000 |
From: William Salmon <will.salmon@codethink.co.uk>
Signed-off-by: William Salmon <will.salmon@codethink.co.uk>
---
target/riscv/helper.h | 1 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvzvkned.c.inc | 1 +
target/riscv/vcrypto_helper.c | 17 +++++++++++++++++
4 files changed, 20 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 58121ba8ad..c55d59dc5e 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1192,6 +1192,7 @@ DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32)
DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32)
DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32)
DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vaesem_vv, void, ptr, ptr, env, i32)
DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32)
DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32)
DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 22059ef95b..f03b41f9e2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -932,6 +932,7 @@ vaesef_vv 101000 1 ..... 00011 010 ..... 1110111
@r2_vm_1
vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1
vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1
vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1
+vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1
vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1
vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1
vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1
diff --git a/target/riscv/insn_trans/trans_rvzvkned.c.inc
b/target/riscv/insn_trans/trans_rvzvkned.c.inc
index 1f59dbcc68..0b54d6e9d3 100644
--- a/target/riscv/insn_trans/trans_rvzvkned.c.inc
+++ b/target/riscv/insn_trans/trans_rvzvkned.c.inc
@@ -95,3 +95,4 @@ GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs)
GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv)
GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs)
GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs)
+GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv)
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
index 41e138ece5..beef7699db 100644
--- a/target/riscv/vcrypto_helper.c
+++ b/target/riscv/vcrypto_helper.c
@@ -241,6 +241,20 @@ static inline void aes_inv_mix_cols(uint8_t
round_state[4][4])
}
}
+static inline void aes_mix_cols(uint8_t round_state[4][4])
+{
+ uint8_t a, b;
+ for (int j = 0; j < 4; ++j) {
+ a = round_state[j][0];
+ b = round_state[j][0] ^ round_state[j][1] ^ round_state[j][2] ^
+ round_state[j][3];
+ round_state[j][0] ^= xtime(round_state[j][0] ^ round_state[j][1]) ^ b;
+ round_state[j][1] ^= xtime(round_state[j][1] ^ round_state[j][2]) ^ b;
+ round_state[j][2] ^= xtime(round_state[j][2] ^ round_state[j][3]) ^ b;
+ round_state[j][3] ^= xtime(round_state[j][3] ^ a) ^ b;
+ }
+}
+
#define GEN_ZVKNED_HELPER_VV(NAME, ...) \
void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \
uint32_t desc) \
@@ -319,6 +333,9 @@ GEN_ZVKNED_HELPER_VV(vaesdf_vv,
aes_inv_shift_bytes(round_state);
GEN_ZVKNED_HELPER_VS(vaesdf_vs, aes_inv_shift_bytes(round_state);
aes_inv_sub_bytes(round_state);
xor_round_key(round_state, (uint8_t *)round_key);)
+GEN_ZVKNED_HELPER_VV(vaesem_vv, aes_shift_bytes(round_state);
+ aes_sub_bytes(round_state); aes_mix_cols(round_state);
+ xor_round_key(round_state, (uint8_t *)round_key);)
GEN_ZVKNED_HELPER_VV(vaesdm_vv, aes_inv_shift_bytes(round_state);
aes_inv_sub_bytes(round_state);
xor_round_key(round_state, (uint8_t *)round_key);
--
2.39.2
- [PATCH 15/45] target/riscv: Expose zvkb cpu property, (continued)
- [PATCH 15/45] target/riscv: Expose zvkb cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 21/45] target/riscv: Add vaesdm.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 17/45] target/riscv: Add vaesef.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 20/45] target/riscv: Add vaesdf.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 22/45] target/riscv: Add vaesdm.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 25/45] target/riscv: Add vaesem.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 27/45] target/riscv: Add vaeskf2.vi decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 29/45] target/riscv: Add zvknh cpu properties, Lawrence Hunter, 2023/03/10
- [PATCH 19/45] target/riscv: Add vaesdf.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 28/45] target/riscv: Expose zvkned cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 24/45] target/riscv: Add vaesem.vv decoding, translation and execution support,
Lawrence Hunter <=
- [PATCH 26/45] target/riscv: Add vaeskf1.vi decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 23/45] target/riscv: Add vaesz.vs decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 32/45] target/riscv: Expose zvknh cpu properties, Lawrence Hunter, 2023/03/10
- [PATCH 43/45] target/riscv: Add zvksed cfg property, Lawrence Hunter, 2023/03/10
- [PATCH 31/45] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 35/45] target/riscv: Add vsm3c.vi decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 34/45] target/riscv: Add vsm3me.vv decoding, translation and execution support, Lawrence Hunter, 2023/03/10
- [PATCH 37/45] target/riscv: Add zvkg cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 40/45] target/riscv: Expose zvkg cpu property, Lawrence Hunter, 2023/03/10
- [PATCH 45/45] target/riscv: Expose Zvksed property, Lawrence Hunter, 2023/03/10