Re: [PATCH 1/2] target/riscv: Expose "virt" register for GDB for reads

[Alistair Francis]

On Sun, Mar 5, 2023 at 7:43 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> This patch enables a debugger to read current virtualization mode via
> virtual "virt" register. After it, we could get full current privilege
> mode via both "priv" and "virt" register.
>
> Extend previous commit ab9056ff9bdb3f95db6e7a666d10522d289f14ec to
> support H-extension.
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>
> Reviewed-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  gdb-xml/riscv-32bit-virtual.xml |  1 +
>  gdb-xml/riscv-64bit-virtual.xml |  1 +
>  target/riscv/gdbstub.c          | 12 ++++++++----
>  3 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/gdb-xml/riscv-32bit-virtual.xml b/gdb-xml/riscv-32bit-virtual.xml
> index 905f1c555d..d44b6ca2dc 100644
> --- a/gdb-xml/riscv-32bit-virtual.xml
> +++ b/gdb-xml/riscv-32bit-virtual.xml
> @@ -8,4 +8,5 @@
>  <!DOCTYPE feature SYSTEM "gdb-target.dtd">
>  <feature name="org.gnu.gdb.riscv.virtual">
>    <reg name="priv" bitsize="32"/>
> +  <reg name="virt" bitsize="32"/>
>  </feature>
> diff --git a/gdb-xml/riscv-64bit-virtual.xml b/gdb-xml/riscv-64bit-virtual.xml
> index 62d86c237b..7c9b63d5b6 100644
> --- a/gdb-xml/riscv-64bit-virtual.xml
> +++ b/gdb-xml/riscv-64bit-virtual.xml
> @@ -8,4 +8,5 @@
>  <!DOCTYPE feature SYSTEM "gdb-target.dtd">
>  <feature name="org.gnu.gdb.riscv.virtual">
>    <reg name="priv" bitsize="64"/>
> +  <reg name="virt" bitsize="64"/>
>  </feature>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 6048541606..1755fd9d51 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -187,13 +187,17 @@ static int riscv_gdb_set_csr(CPURISCVState *env, 
> uint8_t *mem_buf, int n)
>
>  static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)
>  {
> -    if (n == 0) {
>  #ifdef CONFIG_USER_ONLY
> +    if (n >= 0 && n <= 1) {
>          return gdb_get_regl(buf, 0);
> +    }
>  #else
> +    if (n == 0) {
>          return gdb_get_regl(buf, cs->priv);
> -#endif
> +    } else if (n == 1) {
> +        return gdb_get_regl(buf, riscv_cpu_virt_enabled(cs));
>      }
> +#endif
>      return 0;
>  }
>
> @@ -328,13 +332,13 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState 
> *cs)
>      case MXL_RV32:
>          gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
>                                   riscv_gdb_set_virtual,
> -                                 1, "riscv-32bit-virtual.xml", 0);
> +                                 2, "riscv-32bit-virtual.xml", 0);
>          break;
>      case MXL_RV64:
>      case MXL_RV128:
>          gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
>                                   riscv_gdb_set_virtual,
> -                                 1, "riscv-64bit-virtual.xml", 0);
> +                                 2, "riscv-64bit-virtual.xml", 0);
>          break;
>      default:
>          g_assert_not_reached();
> --
> 2.17.1
>
>