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[PULL v2 80/91] target/ppc: Avoid tcg_const_i64 in do_vcntmb
From: |
Richard Henderson |
Subject: |
[PULL v2 80/91] target/ppc: Avoid tcg_const_i64 in do_vcntmb |
Date: |
Thu, 9 Mar 2023 12:05:39 -0800 |
Compute both partial results separately and accumulate
at the end, instead of accumulating in the middle.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate/vmx-impl.c.inc | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index 7af6d7217d..ca27c11d87 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -2236,24 +2236,25 @@ static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b
*a)
static bool do_vcntmb(DisasContext *ctx, arg_VX_mp *a, int vece)
{
- TCGv_i64 rt, vrb, mask;
- rt = tcg_const_i64(0);
- vrb = tcg_temp_new_i64();
+ TCGv_i64 r[2], mask;
+
+ r[0] = tcg_temp_new_i64();
+ r[1] = tcg_temp_new_i64();
mask = tcg_constant_i64(dup_const(vece, 1ULL << ((8 << vece) - 1)));
for (int i = 0; i < 2; i++) {
- get_avr64(vrb, a->vrb, i);
+ get_avr64(r[i], a->vrb, i);
if (a->mp) {
- tcg_gen_and_i64(vrb, mask, vrb);
+ tcg_gen_and_i64(r[i], mask, r[i]);
} else {
- tcg_gen_andc_i64(vrb, mask, vrb);
+ tcg_gen_andc_i64(r[i], mask, r[i]);
}
- tcg_gen_ctpop_i64(vrb, vrb);
- tcg_gen_add_i64(rt, rt, vrb);
+ tcg_gen_ctpop_i64(r[i], r[i]);
}
- tcg_gen_shli_i64(rt, rt, TARGET_LONG_BITS - 8 + vece);
- tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], rt);
+ tcg_gen_add_i64(r[0], r[0], r[1]);
+ tcg_gen_shli_i64(r[0], r[0], TARGET_LONG_BITS - 8 + vece);
+ tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], r[0]);
return true;
}
--
2.34.1
- [PULL v2 75/91] target/arm: Avoid tcg_const_* in translate-mve.c, (continued)
- [PULL v2 75/91] target/arm: Avoid tcg_const_* in translate-mve.c, Richard Henderson, 2023/03/09
- [PULL v2 76/91] target/arm: Avoid tcg_const_ptr in disas_simd_zip_trn, Richard Henderson, 2023/03/09
- [PULL v2 73/91] target/arm: Improve trans_BFCI, Richard Henderson, 2023/03/09
- [PULL v2 85/91] target/ppc: Avoid tcg_const_* in power8-pmu-regs.c.inc, Richard Henderson, 2023/03/09
- [PULL v2 87/91] target/ppc: Fix gen_tlbsx_booke206, Richard Henderson, 2023/03/09
- [PULL v2 91/91] tcg: Drop tcg_const_*, Richard Henderson, 2023/03/09
- [PULL v2 90/91] tcg: Drop tcg_const_*_vec, Richard Henderson, 2023/03/09
- [PULL v2 89/91] target/tricore: Use min/max for saturate, Richard Henderson, 2023/03/09
- [PULL v2 88/91] target/ppc: Avoid tcg_const_* in translate.c, Richard Henderson, 2023/03/09
- [PULL v2 86/91] target/ppc: Rewrite trans_ADDG6S, Richard Henderson, 2023/03/09
- [PULL v2 80/91] target/ppc: Avoid tcg_const_i64 in do_vcntmb,
Richard Henderson <=
- [PULL v2 81/91] target/ppc: Avoid tcg_const_* in vmx-impl.c.inc, Richard Henderson, 2023/03/09
- [PULL v2 83/91] target/ppc: Avoid tcg_const_* in vsx-impl.c.inc, Richard Henderson, 2023/03/09
- [PULL v2 82/91] target/ppc: Avoid tcg_const_* in xxeval, Richard Henderson, 2023/03/09
- [PULL v2 84/91] target/ppc: Avoid tcg_const_* in fp-impl.c.inc, Richard Henderson, 2023/03/09
- Re: [PULL v2 00/91] tcg patch queue, Peter Maydell, 2023/03/11