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[PULL 63/73] hw/pci-bridge/cxl_root_port: Wire up AER
From: |
Michael S. Tsirkin |
Subject: |
[PULL 63/73] hw/pci-bridge/cxl_root_port: Wire up AER |
Date: |
Tue, 7 Mar 2023 20:13:58 -0500 |
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Message-Id: <20230302133709.30373-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c
index 6664783974..00195257f7 100644
--- a/hw/pci-bridge/cxl_root_port.c
+++ b/hw/pci-bridge/cxl_root_port.c
@@ -187,12 +187,15 @@ static void cxl_rp_write_config(PCIDevice *d, uint32_t
address, uint32_t val,
int len)
{
uint16_t slt_ctl, slt_sta;
+ uint32_t root_cmd =
+ pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
pci_bridge_write_config(d, address, val, len);
pcie_cap_flr_write_config(d, address, val, len);
pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
pcie_aer_write_config(d, address, val, len);
+ pcie_aer_root_write_config(d, address, val, len, root_cmd);
cxl_rp_dvsec_write_config(d, address, val, len);
}
--
MST
- [PULL 49/73] tests: acpi: whitelist DSDT before exposing non zero functions, (continued)
- [PULL 49/73] tests: acpi: whitelist DSDT before exposing non zero functions, Michael S. Tsirkin, 2023/03/07
- [PULL 55/73] pci: move acpi-index uniqueness check to generic PCI device code, Michael S. Tsirkin, 2023/03/07
- [PULL 51/73] tests: acpi: update expected blobs, Michael S. Tsirkin, 2023/03/07
- [PULL 56/73] acpi: pci: drop BSEL usage when deciding that device isn't hotpluggable, Michael S. Tsirkin, 2023/03/07
- [PULL 57/73] acpi: pci: move BSEL into build_append_pcihp_slots(), Michael S. Tsirkin, 2023/03/07
- [PULL 59/73] pcihp: move fields enabling hotplug into AcpiPciHpState, Michael S. Tsirkin, 2023/03/07
- [PULL 58/73] acpi: pci: move out ACPI PCI hotplug generator from generic slot generator build_append_pci_bus_devices(), Michael S. Tsirkin, 2023/03/07
- [PULL 60/73] pcihp: add ACPI PCI hotplug specific is_hotpluggable_bus() callback, Michael S. Tsirkin, 2023/03/07
- [PULL 61/73] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register, Michael S. Tsirkin, 2023/03/07
- [PULL 62/73] hw/pci/aer: Add missing routing for AER errors, Michael S. Tsirkin, 2023/03/07
- [PULL 63/73] hw/pci-bridge/cxl_root_port: Wire up AER,
Michael S. Tsirkin <=
- [PULL 64/73] hw/pci-bridge/cxl_root_port: Wire up MSI, Michael S. Tsirkin, 2023/03/07
- [PULL 65/73] hw/mem/cxl-type3: Add AER extended capability, Michael S. Tsirkin, 2023/03/07
- [PULL 66/73] hw/cxl: Fix endian issues in CXL RAS capability defaults / masks, Michael S. Tsirkin, 2023/03/07
- [PULL 67/73] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use., Michael S. Tsirkin, 2023/03/07
- [PULL 68/73] hw/mem/cxl_type3: Add CXL RAS Error Injection Support., Michael S. Tsirkin, 2023/03/07
- [PULL 69/73] hw/pci: Add pcie_count_ds_port() and pcie_find_port_first() helpers, Michael S. Tsirkin, 2023/03/07
- [PULL 71/73] hw/virtio/vhost-user: avoid using unitialized errp, Michael S. Tsirkin, 2023/03/07
- [PULL 70/73] hw/pxb-cxl: Support passthrough HDM Decoders unless overridden, Michael S. Tsirkin, 2023/03/07
- [PULL 72/73] virtio: fix reachable assertion due to stale value of cached region size, Michael S. Tsirkin, 2023/03/07
- [PULL 73/73] virtio: refresh vring region cache after updating a virtqueue size, Michael S. Tsirkin, 2023/03/07