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[PULL 03/20] target/mips: Fix JALS32/J32 instruction handling for microM
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 03/20] target/mips: Fix JALS32/J32 instruction handling for microMIPS |
Date: |
Wed, 8 Mar 2023 00:46:54 +0100 |
From: Marcin Nowakowski <marcin.nowakowski@fungible.com>
microMIPS J & JAL instructions perform a jump in a 128MB region and 5
top bits of the address need to be preserved. This is different behavior
compared to standard mips systems, where the jump is executed within a
256MB region.
Note that microMIPS32 instruction set documentation appears to have
inconsistent information regarding JALX32 instruction - it is written in
the doc that:
"To execute a procedure call within the current 256 MB-aligned region
(...)
The low 26 bits of the target address is the target field shifted left
2 bits."
But the target address is already 26 bits. Moreover, the operation
description indicates that 28 bits are copied, so the statement about
use of 26 bits is _most likely_ incorrect and the corresponding code
remains the same as for standard mips instruction set.
Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230216051717.3911212-2-marcin.nowakowski@fungible.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/mips/tcg/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 8cad3d15a0..24993bc97d 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -4887,6 +4887,14 @@ static void gen_compute_branch(DisasContext *ctx,
uint32_t opc,
break;
case OPC_J:
case OPC_JAL:
+ {
+ /* Jump to immediate */
+ int jal_mask = ctx->hflags & MIPS_HFLAG_M16 ? 0xF8000000
+ : 0xF0000000;
+ btgt = ((ctx->base.pc_next + insn_bytes) & jal_mask)
+ | (uint32_t)offset;
+ break;
+ }
case OPC_JALX:
/* Jump to immediate */
btgt = ((ctx->base.pc_next + insn_bytes) & (int32_t)0xF0000000) |
--
2.38.1
- [PULL 00/20] MIPS patches for 2023-03-07, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 01/20] docs/system: Remove "mips" board from target-mips.rst, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 02/20] target/mips: Replace [g_]assert(0) -> g_assert_not_reached(), Philippe Mathieu-Daudé, 2023/03/07
- [PULL 03/20] target/mips: Fix JALS32/J32 instruction handling for microMIPS,
Philippe Mathieu-Daudé <=
- [PULL 04/20] target/mips: Fix SWM32 handling for microMIPS, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 05/20] target/mips: Implement CP0.Config7.WII bit support, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 06/20] target/mips: Set correct CP0.Config[4, 5] values for M14K(c), Philippe Mathieu-Daudé, 2023/03/07
- [PULL 07/20] hw/mips: Declare all length properties as unsigned, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 08/20] hw/mips/itu: Pass SAAR using QOM link property, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 09/20] Revert "hw/isa/i82378: Remove intermediate IRQ forwarder", Philippe Mathieu-Daudé, 2023/03/07
- [PULL 10/20] Revert "hw/isa/vt82c686: Remove intermediate IRQ forwarder", Philippe Mathieu-Daudé, 2023/03/07
- [PULL 11/20] hw/display/sm501: Add debug property to control pixman usage, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 12/20] hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select, Philippe Mathieu-Daudé, 2023/03/07
- [PULL 13/20] hw/isa/vt82c686: Implement PCI IRQ routing, Philippe Mathieu-Daudé, 2023/03/07