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[PULL 59/67] target/sh4: Avoid tcg_const_i32 for TAS.B
From: |
Richard Henderson |
Subject: |
[PULL 59/67] target/sh4: Avoid tcg_const_i32 for TAS.B |
Date: |
Tue, 7 Mar 2023 09:58:40 -0800 |
Since we're assigning to cpu_sr_t in the end,
use that as the intermediate temp as well.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sh4/translate.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index ad6de41712..70a45c26e8 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -1610,12 +1610,9 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
return;
case 0x401b: /* tas.b @Rn */
- {
- TCGv val = tcg_const_i32(0x80);
- tcg_gen_atomic_fetch_or_i32(val, REG(B11_8), val,
- ctx->memidx, MO_UB);
- tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0);
- }
+ tcg_gen_atomic_fetch_or_i32(cpu_sr_t, REG(B11_8),
+ tcg_constant_i32(0x80), ctx->memidx,
MO_UB);
+ tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, cpu_sr_t, 0);
return;
case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
CHECK_FPU_ENABLED
--
2.34.1
- [PULL 48/67] target/mips: Split out gen_lxl, (continued)
- [PULL 48/67] target/mips: Split out gen_lxl, Richard Henderson, 2023/03/07
- [PULL 49/67] target/mips: Split out gen_lxr, Richard Henderson, 2023/03/07
- [PULL 52/67] target/ppc: Split out gen_vx_vmul10, Richard Henderson, 2023/03/07
- [PULL 51/67] target/mips: Avoid tcg_const_* throughout, Richard Henderson, 2023/03/07
- [PULL 55/67] target/rx: Use cpu_psw_z as temp in flags computation, Richard Henderson, 2023/03/07
- [PULL 50/67] target/mips: Avoid tcg_const_tl in gen_r6_ld, Richard Henderson, 2023/03/07
- [PULL 54/67] target/rx: Use tcg_gen_abs_i32, Richard Henderson, 2023/03/07
- [PULL 56/67] target/rx: Avoid tcg_const_i32 when new temp needed, Richard Henderson, 2023/03/07
- [PULL 47/67] target/m68k: Avoid tcg_const_* throughout, Richard Henderson, 2023/03/07
- [PULL 57/67] target/rx: Avoid tcg_const_i32, Richard Henderson, 2023/03/07
- [PULL 59/67] target/sh4: Avoid tcg_const_i32 for TAS.B,
Richard Henderson <=
- [PULL 60/67] target/sh4: Avoid tcg_const_i32, Richard Henderson, 2023/03/07
- [PULL 53/67] target/ppc: Avoid tcg_const_i64 in do_vector_shift_quad, Richard Henderson, 2023/03/07
- [PULL 58/67] target/s390x: Avoid tcg_const_i64, Richard Henderson, 2023/03/07
- [PULL 61/67] tcg/sparc: Avoid tcg_const_tl in gen_edge, Richard Henderson, 2023/03/07
- [PULL 62/67] target/tricore: Split t_n as constant from temp as variable, Richard Henderson, 2023/03/07
- [PULL 64/67] target/tricore: Use setcondi instead of explicit allocation, Richard Henderson, 2023/03/07
- [PULL 65/67] target/tricore: Drop some temp initialization, Richard Henderson, 2023/03/07
- [PULL 66/67] target/tricore: Avoid tcg_const_i32, Richard Henderson, 2023/03/07
- [PULL 63/67] target/tricore: Rename t_off10 and use tcg_constant_i32, Richard Henderson, 2023/03/07
- [PULL 67/67] tcg: Replace tcg_const_i64 in tcg-op.c, Richard Henderson, 2023/03/07