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[PATCH v12 08/10] target/riscv: expose properties for Zc* extension
From: |
Weiwei Li |
Subject: |
[PATCH v12 08/10] target/riscv: expose properties for Zc* extension |
Date: |
Tue, 7 Mar 2023 16:14:01 +0800 |
Expose zca,zcb,zcf,zcd,zcmp,zcmt properties.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index df7eed57af..d17ae942bd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -87,6 +87,12 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin),
ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx),
ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx),
+ ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca),
+ ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb),
+ ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf),
+ ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd),
+ ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp),
+ ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt),
ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba),
ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb),
ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc),
@@ -1491,6 +1497,14 @@ static Property riscv_cpu_extensions[] = {
/* These are experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
+
+ DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false),
+ DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false),
+ DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false),
+ DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false),
+ DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false),
+ DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false),
+
/* ePMP 0.9.3 */
DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
--
2.25.1
- [PATCH v12 00/10] support subsets of code size reduction extension, Weiwei Li, 2023/03/07
- [PATCH v12 05/10] target/riscv: add support for Zcb extension, Weiwei Li, 2023/03/07
- [PATCH v12 03/10] target/riscv: add support for Zcf extension, Weiwei Li, 2023/03/07
- [PATCH v12 04/10] target/riscv: add support for Zcd extension, Weiwei Li, 2023/03/07
- [PATCH v12 10/10] target/riscv: Add support for Zce, Weiwei Li, 2023/03/07
- [PATCH v12 07/10] target/riscv: add support for Zcmt extension, Weiwei Li, 2023/03/07
- [PATCH v12 01/10] target/riscv: add cfg properties for Zc* extension, Weiwei Li, 2023/03/07
- [PATCH v12 02/10] target/riscv: add support for Zca extension, Weiwei Li, 2023/03/07
- [PATCH v12 06/10] target/riscv: add support for Zcmp extension, Weiwei Li, 2023/03/07
- [PATCH v12 08/10] target/riscv: expose properties for Zc* extension,
Weiwei Li <=
- [PATCH v12 09/10] disas/riscv.c: add disasm support for Zc*, Weiwei Li, 2023/03/07
- Re: [PATCH v12 00/10] support subsets of code size reduction extension, liweiwei, 2023/03/24