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[PATCH v7 3/6] hw/isa/vt82c686: Implement PCI IRQ routing
From: |
BALATON Zoltan |
Subject: |
[PATCH v7 3/6] hw/isa/vt82c686: Implement PCI IRQ routing |
Date: |
Sun, 5 Mar 2023 15:05:49 +0100 (CET) |
The real VIA south bridges implement a PCI IRQ router which is configured
by the BIOS or the OS. In order to respect these configurations, QEMU
needs to implement it as well. The real chip may allow routing IRQs from
internal functions independently of PCI interrupts but since guests
usually configute it to a single shared interrupt we don't model that
here for simplicity.
Note: The implementation was taken from piix4_set_irq() in hw/isa/piix4.
Suggested-by: Bernhard Beschow <shentey@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Tested-by: Rene Engel <ReneEngel80@emailn.de>
---
hw/isa/vt82c686.c | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 8900d87f59..e5aa467506 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -600,6 +600,46 @@ void via_isa_set_irq(PCIDevice *d, int n, int level)
qemu_set_irq(s->isa_irqs_in[n], level);
}
+static int via_isa_get_pci_irq(const ViaISAState *s, int irq_num)
+{
+ switch (irq_num) {
+ case 0:
+ return s->dev.config[0x55] >> 4;
+ case 1:
+ return s->dev.config[0x56] & 0xf;
+ case 2:
+ return s->dev.config[0x56] >> 4;
+ case 3:
+ return s->dev.config[0x57] >> 4;
+ }
+ return 0;
+}
+
+static void via_isa_set_pci_irq(void *opaque, int irq_num, int level)
+{
+ ViaISAState *s = opaque;
+ PCIBus *bus = pci_get_bus(&s->dev);
+ int i, pic_level, pic_irq = via_isa_get_pci_irq(s, irq_num);
+
+ /* IRQ 0 and 15 mean disabled, IRQ 2 is reserved */
+ if (unlikely(pic_irq == 0 || pic_irq == 2 || pic_irq > 14)) {
+ if (pic_irq == 2) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid ISA IRQ routing");
+ }
+ return;
+ }
+
+ /* The pic level is the logical OR of all the PCI irqs mapped to it. */
+ pic_level = 0;
+ for (i = 0; i < PCI_NUM_PINS; i++) {
+ if (pic_irq == via_isa_get_pci_irq(s, i)) {
+ pic_level |= pci_bus_get_irq_level(bus, i);
+ }
+ }
+ /* Now we change the pic irq level according to the via irq mappings. */
+ qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level);
+}
+
static void via_isa_realize(PCIDevice *d, Error **errp)
{
ViaISAState *s = VIA_ISA(d);
@@ -620,6 +660,8 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
i8254_pit_init(isa_bus, 0x40, 0, NULL);
i8257_dma_init(isa_bus, 0);
+ qdev_init_gpio_in_named(dev, via_isa_set_pci_irq, "pirq", PCI_NUM_PINS);
+
/* RTC */
qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
--
2.30.8
[PATCH v7 2/6] hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select, BALATON Zoltan, 2023/03/05
[PATCH v7 1/6] hw/display/sm501: Add debug property to control pixman usage, BALATON Zoltan, 2023/03/05
[PATCH v7 4/6] hw/ppc/pegasos2: Fix PCI interrupt routing, BALATON Zoltan, 2023/03/05
[PATCH v7 6/6] hw/audio/via-ac97: Basic implementation of audio playback, BALATON Zoltan, 2023/03/05
[PATCH v7 5/6] hw/usb/vt82c686-uhci-pci: Use PCI IRQ routing, BALATON Zoltan, 2023/03/05
Re: [PATCH v7 0/6] Pegasos2 fixes and audio output support, BALATON Zoltan, 2023/03/05