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[PULL 32/59] target/riscv: Simplify {read, write}_pmpcfg() a little bit
From: |
Palmer Dabbelt |
Subject: |
[PULL 32/59] target/riscv: Simplify {read, write}_pmpcfg() a little bit |
Date: |
Fri, 3 Mar 2023 00:37:13 -0800 |
From: Bin Meng <bmeng@tinylab.org>
Use the register index that has already been calculated in the
pmpcfg_csr_{read,write} call.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-9-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/csr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9264db6110..a3e0e5755c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3360,7 +3360,7 @@ static RISCVException read_pmpcfg(CPURISCVState *env, int
csrno,
if (!check_pmp_reg_index(env, reg_index)) {
return RISCV_EXCP_ILLEGAL_INST;
}
- *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
+ *val = pmpcfg_csr_read(env, reg_index);
return RISCV_EXCP_NONE;
}
@@ -3372,7 +3372,7 @@ static RISCVException write_pmpcfg(CPURISCVState *env,
int csrno,
if (!check_pmp_reg_index(env, reg_index)) {
return RISCV_EXCP_ILLEGAL_INST;
}
- pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
+ pmpcfg_csr_write(env, reg_index, val);
return RISCV_EXCP_NONE;
}
--
2.39.2
- [PULL 21/59] target/riscv: Add support for Zvfh/zvfhmin extensions, (continued)
- [PULL 21/59] target/riscv: Add support for Zvfh/zvfhmin extensions, Palmer Dabbelt, 2023/03/03
- [PULL 22/59] target/riscv: Fix check for vector load/store instructions when EEW=64, Palmer Dabbelt, 2023/03/03
- [PULL 23/59] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc, Palmer Dabbelt, 2023/03/03
- [PULL 25/59] target/riscv: gdbstub: Check priv spec version before reporting CSR, Palmer Dabbelt, 2023/03/03
- [PULL 24/59] target/riscv: Expose properties for Zv* extensions, Palmer Dabbelt, 2023/03/03
- [PULL 26/59] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check(), Palmer Dabbelt, 2023/03/03
- [PULL 27/59] target/riscv: Use g_assert() for the predicate() NULL check, Palmer Dabbelt, 2023/03/03
- [PULL 28/59] target/riscv: gdbstub: Minor change for better readability, Palmer Dabbelt, 2023/03/03
- [PULL 29/59] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled, Palmer Dabbelt, 2023/03/03
- [PULL 31/59] target/riscv: Use 'bool' type for read_only, Palmer Dabbelt, 2023/03/03
- [PULL 32/59] target/riscv: Simplify {read, write}_pmpcfg() a little bit,
Palmer Dabbelt <=
- [PULL 34/59] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64, Palmer Dabbelt, 2023/03/03
- [PULL 36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml, Palmer Dabbelt, 2023/03/03
- [PULL 35/59] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate(), Palmer Dabbelt, 2023/03/03
- [PULL 30/59] target/riscv: Coding style fixes in csr.c, Palmer Dabbelt, 2023/03/03
- [PULL 33/59] target/riscv: Simplify getting RISCVCPU pointer from env, Palmer Dabbelt, 2023/03/03
- [PULL 39/59] target/riscv: Allow debugger to access {h, s}stateen CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 37/59] target/riscv: Allow debugger to access user timer and counter CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 40/59] target/riscv: Allow debugger to access sstc CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 41/59] target/riscv: Drop priv level check in mseccfg predicate(), Palmer Dabbelt, 2023/03/03
- [PULL 43/59] target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages, Palmer Dabbelt, 2023/03/03