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[PULL 23/59] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.in
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From: |
Palmer Dabbelt |
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Subject: |
[PULL 23/59] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc |
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Date: |
Fri, 3 Mar 2023 00:37:04 -0800 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
Only V extension supports EEW = 64 in these cases: Zve64* extensions don't
support EEW = 64 in these cases as commented before the check.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-14-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 5dbdce073b..fc0d0d60e8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1998,8 +1998,7 @@ static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)
* are not included for EEW=64 in Zve64*. (Section 18.2)
*/
return opivv_check(s, a) &&
- (!has_ext(s, RVV) &&
- s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+ (!has_ext(s, RVV) ? s->sew != MO_64 : true);
}
static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
@@ -2012,8 +2011,7 @@ static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)
* are not included for EEW=64 in Zve64*. (Section 18.2)
*/
return opivx_check(s, a) &&
- (!has_ext(s, RVV) &&
- s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+ (!has_ext(s, RVV) ? s->sew != MO_64 : true);
}
GEN_OPIVV_GVEC_TRANS(vmul_vv, mul)
@@ -2230,8 +2228,7 @@ static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)
* for EEW=64 in Zve64*. (Section 18.2)
*/
return opivv_check(s, a) &&
- (!has_ext(s, RVV) &&
- s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+ (!has_ext(s, RVV) ? s->sew != MO_64 : true);
}
static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
@@ -2242,8 +2239,7 @@ static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)
* for EEW=64 in Zve64*. (Section 18.2)
*/
return opivx_check(s, a) &&
- (!has_ext(s, RVV) &&
- s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+ (!has_ext(s, RVV) ? s->sew != MO_64 : true);
}
GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)
--
2.39.2
- [PULL 14/59] target/riscv: Add cfg properties for Zv* extensions, (continued)
- [PULL 14/59] target/riscv: Add cfg properties for Zv* extensions, Palmer Dabbelt, 2023/03/03
- [PULL 15/59] target/riscv: Fix relationship between V, Zve*, F and D, Palmer Dabbelt, 2023/03/03
- [PULL 16/59] target/riscv: Add property check for Zvfh{min} extensions, Palmer Dabbelt, 2023/03/03
- [PULL 17/59] target/riscv: Indent fixes in cpu.c, Palmer Dabbelt, 2023/03/03
- [PULL 18/59] target/riscv: Simplify check for Zve32f and Zve64f, Palmer Dabbelt, 2023/03/03
- [PULL 12/59] target/riscv: Fix the relationship between Zhinxmin and Zhinx, Palmer Dabbelt, 2023/03/03
- [PULL 19/59] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc, Palmer Dabbelt, 2023/03/03
- [PULL 20/59] target/riscv: Remove redundunt check for zve32f and zve64f, Palmer Dabbelt, 2023/03/03
- [PULL 21/59] target/riscv: Add support for Zvfh/zvfhmin extensions, Palmer Dabbelt, 2023/03/03
- [PULL 22/59] target/riscv: Fix check for vector load/store instructions when EEW=64, Palmer Dabbelt, 2023/03/03
- [PULL 23/59] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc,
Palmer Dabbelt <=
- [PULL 25/59] target/riscv: gdbstub: Check priv spec version before reporting CSR, Palmer Dabbelt, 2023/03/03
- [PULL 24/59] target/riscv: Expose properties for Zv* extensions, Palmer Dabbelt, 2023/03/03
- [PULL 26/59] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check(), Palmer Dabbelt, 2023/03/03
- [PULL 27/59] target/riscv: Use g_assert() for the predicate() NULL check, Palmer Dabbelt, 2023/03/03
- [PULL 28/59] target/riscv: gdbstub: Minor change for better readability, Palmer Dabbelt, 2023/03/03
- [PULL 29/59] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled, Palmer Dabbelt, 2023/03/03
- [PULL 31/59] target/riscv: Use 'bool' type for read_only, Palmer Dabbelt, 2023/03/03
- [PULL 32/59] target/riscv: Simplify {read, write}_pmpcfg() a little bit, Palmer Dabbelt, 2023/03/03
- [PULL 34/59] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64, Palmer Dabbelt, 2023/03/03
- [PULL 36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml, Palmer Dabbelt, 2023/03/03