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[PULL 08/59] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt
From: |
Palmer Dabbelt |
Subject: |
[PULL 08/59] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus() |
Date: |
Fri, 3 Mar 2023 00:36:49 -0800 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Read cpu_ptr->cfg.mmu directly. As a bonus, use cpu_ptr in
riscv_isa_string().
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230222185205.355361-9-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
hw/riscv/virt.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 86c4adc0c9..49f2c157f7 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -232,20 +232,21 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int
socket,
bool is_32_bit = riscv_is_32bit(&s->soc[0]);
for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
+ RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu];
+
cpu_phandle = (*phandle)++;
cpu_name = g_strdup_printf("/cpus/cpu@%d",
s->soc[socket].hartid_base + cpu);
qemu_fdt_add_subnode(ms->fdt, cpu_name);
- if (riscv_feature(&s->soc[socket].harts[cpu].env,
- RISCV_FEATURE_MMU)) {
+ if (cpu_ptr->cfg.mmu) {
qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
(is_32_bit) ? "riscv,sv32" : "riscv,sv48");
} else {
qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
"riscv,none");
}
- name = riscv_isa_string(&s->soc[socket].harts[cpu]);
+ name = riscv_isa_string(cpu_ptr);
qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
g_free(name);
qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
--
2.39.2
- [PULL 01/59] target/riscv: introduce riscv_cpu_cfg(), (continued)
- [PULL 01/59] target/riscv: introduce riscv_cpu_cfg(), Palmer Dabbelt, 2023/03/03
- [PULL 02/59] target/riscv: do not mask unsupported QEMU extensions in write_misa(), Palmer Dabbelt, 2023/03/03
- [PULL 03/59] target/riscv: allow MISA writes as experimental, Palmer Dabbelt, 2023/03/03
- [PULL 04/59] target/riscv: remove RISCV_FEATURE_DEBUG, Palmer Dabbelt, 2023/03/03
- [PULL 05/59] target/riscv/cpu.c: error out if EPMP is enabled without PMP, Palmer Dabbelt, 2023/03/03
- [PULL 07/59] target/riscv: remove RISCV_FEATURE_PMP, Palmer Dabbelt, 2023/03/03
- [PULL 09/59] target/riscv: remove RISCV_FEATURE_MMU, Palmer Dabbelt, 2023/03/03
- [PULL 10/59] target/riscv/cpu: remove CPUArchState::features and friends, Palmer Dabbelt, 2023/03/03
- [PULL 06/59] target/riscv: remove RISCV_FEATURE_EPMP, Palmer Dabbelt, 2023/03/03
- [PULL 11/59] target/riscv: Fix the relationship between Zfhmin and Zfh, Palmer Dabbelt, 2023/03/03
- [PULL 08/59] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus(),
Palmer Dabbelt <=
- [PULL 13/59] target/riscv: Simplify the check for Zfhmin and Zhinxmin, Palmer Dabbelt, 2023/03/03
- [PULL 14/59] target/riscv: Add cfg properties for Zv* extensions, Palmer Dabbelt, 2023/03/03
- [PULL 15/59] target/riscv: Fix relationship between V, Zve*, F and D, Palmer Dabbelt, 2023/03/03
- [PULL 16/59] target/riscv: Add property check for Zvfh{min} extensions, Palmer Dabbelt, 2023/03/03
- [PULL 17/59] target/riscv: Indent fixes in cpu.c, Palmer Dabbelt, 2023/03/03
- [PULL 18/59] target/riscv: Simplify check for Zve32f and Zve64f, Palmer Dabbelt, 2023/03/03
- [PULL 12/59] target/riscv: Fix the relationship between Zhinxmin and Zhinx, Palmer Dabbelt, 2023/03/03
- [PULL 19/59] target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc, Palmer Dabbelt, 2023/03/03
- [PULL 20/59] target/riscv: Remove redundunt check for zve32f and zve64f, Palmer Dabbelt, 2023/03/03
- [PULL 21/59] target/riscv: Add support for Zvfh/zvfhmin extensions, Palmer Dabbelt, 2023/03/03