Re: [PATCH v3 4/8] hw/isa/vt82c686: Implement PCI IRQ routing

[BALATON Zoltan]

On Wed, 1 Mar 2023, Mark Cave-Ayland wrote:
> On 27/02/2023 16:52, Bernhard Beschow wrote:
> > On Mon, Feb 27, 2023 at 1:57 PM BALATON Zoltan <balaton@eik.bme.hu 
> > <mailto:balaton@eik.bme.hu>> wrote:
> > in. So if
> >      >> fuloon2e needs to do that then it should. I'll check that as I was 
> > focusing
> >      >
> >      > fuloong2e
> >
> >     I've checked fuloong2e and it still works as before. PCI bus is handled by
> >     bonito on that board so your patch would actually break it. The VIA chip
> >     is a PCIDevice. You're not supposed to replace the interrupts of the bus
> >     it's connected to from this model as that should be done by the pci-host
> >     or the board. Therefore modeling the chip's PIRQ/PINT pins as gpios which
> >     is the QDev concept for that is right and your usage of pci_set_irq here
> >     is wrong.
> >
> >
> > Works for me:
> > (08/84) 
> > tests/avocado/boot_linux_console.py:BootLinuxConsole.test_mips64el_fuloong2e: 
> > PASS(2.77 s)
>
> The bonito code is interesting in that the IRQ is swizzled in 
> pci_bonito_map_irq() to the internal IRQ, and then pci_bonito_set_irq() sets 
> the output (CPU?) IRQ accordingly. This means that the routing is currently 
> fixed based upon the slot number, rather than using the VIA PCI IRQ routing. 
> This bit will need some thought as to how this interacts with pci_bus_irqs() 
> in your proposed patch, feel free to suggest a suitable approach.

I believe the fuloong2e may be similarly connected as the pegasos2. The 
Marvell Discovery II mv64361 was based on a MIPS counterpart so the 
concepts may be similar in these just the CPU arch is different.

This doc https://wiki.qemu.org/images/0/09/Bonito64-spec.pdf says the 
bonito north bridge has some GPin and GPIO pins which are connected to the 
interrupt controller (see section 5.15). Probably you can infer which pins 
PCI IRQs should come in from the map_irq function in the bonito model. I'd 
expect GPIO0-3 based on description in the table in section 6.1

On the other hand the board's firmware suggests PCI interrupt lines are 
also connected to the PIRQ pins of th 686B:

https://github.com/loongson-community/pmon/blob/master/sys/dev/pci/vt82c686_devbd2e.c

(if this is the right file to look at as there are different versions but 
dev board 2e said to inlude fuloong2e in the main README). Then in 686B 
PCI interrupts are mapped to 9.10.11.13 with the PnP IRQ routing registers 
in 686B.

This could then be modeled similarly to how I did it in this series for 
pegasos2: One could add gpio inputs in bonito to model the pins where the 
PCI interrupt lines are connected then connect these together in the board 
code just like they are wired on the real board.

Although this board does not have any PCI slots so these are only for the 
on board PCI devices: https://www.linux-mips.org/wiki/Fuloong_2E but a 
similar dev board may have 4 PCI slots.

Regards,
BALATON Zoltan