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[PULL 10/62] target/arm: Replace `TARGET_TB_PCREL` with `CF_PCREL`
From: |
Richard Henderson |
Subject: |
[PULL 10/62] target/arm: Replace `TARGET_TB_PCREL` with `CF_PCREL` |
Date: |
Tue, 28 Feb 2023 16:55:51 -1000 |
From: Anton Johansson via <qemu-devel@nongnu.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230227135202.9710-7-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate.h | 2 +-
target/arm/cpu.c | 8 ++++----
target/arm/tcg/translate-a64.c | 8 ++++----
target/arm/tcg/translate.c | 6 +++---
4 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 3717824b75..4001372acd 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -23,7 +23,7 @@ typedef struct DisasContext {
/* The address of the current instruction being translated. */
target_ulong pc_curr;
/*
- * For TARGET_TB_PCREL, the full value of cpu_pc is not known
+ * For CF_PCREL, the full value of cpu_pc is not known
* (although the page offset is known). For convenience, the
* translation loop uses the full virtual address that triggered
* the translation, from base.pc_start through pc_curr.
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b21d52cce7..850b018efb 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -78,8 +78,8 @@ static vaddr arm_cpu_get_pc(CPUState *cs)
void arm_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
- /* The program counter is always up to date with TARGET_TB_PCREL. */
- if (!TARGET_TB_PCREL) {
+ /* The program counter is always up to date with CF_PCREL. */
+ if (!(tb_cflags(tb) & CF_PCREL)) {
CPUARMState *env = cs->env_ptr;
/*
* It's OK to look at env for the current mode here, because it's
@@ -100,7 +100,7 @@ void arm_restore_state_to_opc(CPUState *cs,
CPUARMState *env = cs->env_ptr;
if (is_a64(env)) {
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(tb) & CF_PCREL) {
env->pc = (env->pc & TARGET_PAGE_MASK) | data[0];
} else {
env->pc = data[0];
@@ -108,7 +108,7 @@ void arm_restore_state_to_opc(CPUState *cs,
env->condexec_bits = 0;
env->exception.syndrome = data[2] << ARM_INSN_START_WORD2_SHIFT;
} else {
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(tb) & CF_PCREL) {
env->regs[15] = (env->regs[15] & TARGET_PAGE_MASK) | data[0];
} else {
env->regs[15] = data[0];
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 67e9c4ee79..7bbffdd1fe 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -143,7 +143,7 @@ static void reset_btype(DisasContext *s)
static void gen_pc_plus_diff(DisasContext *s, TCGv_i64 dest, target_long diff)
{
assert(s->pc_save != -1);
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(s->base.tb) & CF_PCREL) {
tcg_gen_addi_i64(dest, cpu_pc, (s->pc_curr - s->pc_save) + diff);
} else {
tcg_gen_movi_i64(dest, s->pc_curr + diff);
@@ -393,7 +393,7 @@ static void gen_goto_tb(DisasContext *s, int n, int64_t
diff)
* update to pc to the unlinked path. A long chain of links
* can thus avoid many updates to the PC.
*/
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(s->base.tb) & CF_PCREL) {
gen_a64_update_pc(s, diff);
tcg_gen_goto_tb(n);
} else {
@@ -4297,7 +4297,7 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t
insn)
if (page) {
/* ADRP (page based) */
offset <<= 12;
- /* The page offset is ok for TARGET_TB_PCREL. */
+ /* The page offset is ok for CF_PCREL. */
offset -= s->pc_curr & 0xfff;
}
@@ -14809,7 +14809,7 @@ static void aarch64_tr_insn_start(DisasContextBase
*dcbase, CPUState *cpu)
DisasContext *dc = container_of(dcbase, DisasContext, base);
target_ulong pc_arg = dc->base.pc_next;
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(dcbase->tb) & CF_PCREL) {
pc_arg &= ~TARGET_PAGE_MASK;
}
tcg_gen_insn_start(pc_arg, 0, 0);
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index c23a3462bf..0e7d3b8561 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -269,7 +269,7 @@ static target_long jmp_diff(DisasContext *s, target_long
diff)
static void gen_pc_plus_diff(DisasContext *s, TCGv_i32 var, target_long diff)
{
assert(s->pc_save != -1);
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(s->base.tb) & CF_PCREL) {
tcg_gen_addi_i32(var, cpu_R[15], (s->pc_curr - s->pc_save) + diff);
} else {
tcg_gen_movi_i32(var, s->pc_curr + diff);
@@ -2620,7 +2620,7 @@ static void gen_goto_tb(DisasContext *s, int n,
target_long diff)
* update to pc to the unlinked path. A long chain of links
* can thus avoid many updates to the PC.
*/
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(s->base.tb) & CF_PCREL) {
gen_update_pc(s, diff);
tcg_gen_goto_tb(n);
} else {
@@ -9542,7 +9542,7 @@ static void arm_tr_insn_start(DisasContextBase *dcbase,
CPUState *cpu)
uint32_t condexec_bits;
target_ulong pc_arg = dc->base.pc_next;
- if (TARGET_TB_PCREL) {
+ if (tb_cflags(dcbase->tb) & CF_PCREL) {
pc_arg &= ~TARGET_PAGE_MASK;
}
if (dc->eci) {
--
2.34.1
- [PULL 00/62] tcg patch queue, Richard Henderson, 2023/02/28
- [PULL 01/62] exec/helper-head: Include missing "fpu/softfloat-types.h" header, Richard Henderson, 2023/02/28
- [PULL 02/62] softmmu: Use memmove in flatview_write_continue, Richard Henderson, 2023/02/28
- [PULL 03/62] accel/tcg: Add 'size' param to probe_access_flags(), Richard Henderson, 2023/02/28
- [PULL 04/62] accel/tcg: Add 'size' param to probe_access_full, Richard Henderson, 2023/02/28
- [PULL 05/62] include/exec: Introduce `CF_PCREL`, Richard Henderson, 2023/02/28
- [PULL 06/62] target/i386: set `CF_PCREL` in `x86_cpu_realizefn`, Richard Henderson, 2023/02/28
- [PULL 07/62] target/arm: set `CF_PCREL` in `arm_cpu_realizefn`, Richard Henderson, 2023/02/28
- [PULL 10/62] target/arm: Replace `TARGET_TB_PCREL` with `CF_PCREL`,
Richard Henderson <=
- [PULL 08/62] accel/tcg: Replace `TARGET_TB_PCREL` with `CF_PCREL`, Richard Henderson, 2023/02/28
- [PULL 13/62] target/arm: Remove `TARGET_TB_PCREL` define, Richard Henderson, 2023/02/28
- [PULL 09/62] include/exec: Replace `TARGET_TB_PCREL` with `CF_PCREL`, Richard Henderson, 2023/02/28
- [PULL 14/62] target/i386: Remove `TARGET_TB_PCREL` define, Richard Henderson, 2023/02/28
- [PULL 11/62] target/i386: Replace `TARGET_TB_PCREL` with `CF_PCREL`, Richard Henderson, 2023/02/28
- [PULL 12/62] include/exec: Remove `TARGET_TB_PCREL` define, Richard Henderson, 2023/02/28
- [PULL 18/62] target/sparc: Replace `tb_pc()` with `tb->pc`, Richard Henderson, 2023/02/28
- [PULL 16/62] accel/tcg: Replace `tb_pc()` with `tb->pc`, Richard Henderson, 2023/02/28
- [PULL 20/62] target/rx: Replace `tb_pc()` with `tb->pc`, Richard Henderson, 2023/02/28
- [PULL 17/62] target/tricore: Replace `tb_pc()` with `tb->pc`, Richard Henderson, 2023/02/28