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[PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access
From: |
Bin Meng |
Subject: |
[PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access |
Date: |
Tue, 28 Feb 2023 18:40:16 +0800 |
At present gdbstub reports an incorrect / incomplete CSR list in the
target description XML, for example:
- menvcfg is reported in 'sifive_u' machine
- fcsr is missing in a F/D enabled processor
The issue is caused by:
- priv spec version check is missing when reporting CSRs
- CSR predicate() routine is called without turning on the debugger flag
This series aims to generate a correct and complete CSR list for gdbstub.
This series is rebased against Daniel's FEATURE_* clean-up series v7.
Based-on: 20230222185205.355361-1-dbarboza@ventanamicro.com
Changes in v2:
- keep the original priority policy, instead add some comments for clarification
- new patch: Use assert() for the predicate() NULL check
- keep the 'RV128 restriction check' todo comment
- move smstateen_acc_ok() to near {read,write}_xenvcfg()
- drop patch "target/riscv: Move configuration check to envcfg CSRs predicate()"
Bin Meng (18):
target/riscv: gdbstub: Check priv spec version before reporting CSR
target/riscv: Add some comments to clarify the priority policy of
riscv_csrrw_check()
target/riscv: Use g_assert() for the predicate() NULL check
target/riscv: gdbstub: Minor change for better readability
target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
target/riscv: Coding style fixes in csr.c
target/riscv: Use 'bool' type for read_only
target/riscv: Simplify {read,write}_pmpcfg() a little bit
target/riscv: Simplify getting RISCVCPU pointer from env
target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for
RV64
target/riscv: gdbstub: Turn on debugger mode before calling CSR
predicate()
target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml
target/riscv: Allow debugger to access user timer and counter CSRs
target/riscv: Allow debugger to access seed CSR
target/riscv: Allow debugger to access {h,s}stateen CSRs
target/riscv: Allow debugger to access sstc CSRs
target/riscv: Drop priv level check in mseccfg predicate()
target/riscv: Group all predicate() routines together
target/riscv/csr.c | 341 ++++++++++++++++++++++-------------------
target/riscv/gdbstub.c | 100 +++---------
2 files changed, 201 insertions(+), 240 deletions(-)
--
2.25.1
- [PATCH v2 00/18] target/riscv: Various fixes to gdbstub and CSR access,
Bin Meng <=
- [PATCH v2 01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR, Bin Meng, 2023/02/28
- [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check(), Bin Meng, 2023/02/28
- [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check, Bin Meng, 2023/02/28
- [PATCH v2 04/18] target/riscv: gdbstub: Minor change for better readability, Bin Meng, 2023/02/28
- [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled, Bin Meng, 2023/02/28
- [PATCH v2 06/18] target/riscv: Coding style fixes in csr.c, Bin Meng, 2023/02/28
- [PATCH v2 07/18] target/riscv: Use 'bool' type for read_only, Bin Meng, 2023/02/28
- [PATCH v2 08/18] target/riscv: Simplify {read, write}_pmpcfg() a little bit, Bin Meng, 2023/02/28