Re: [PATCH 4/4] target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig

[liweiwei]

On 2023/2/25 01:45, Daniel Henrique Barboza wrote:
> Retrieving the CPU pointer using env_archcpu() just to access cpu->cfg
> can be avoided by using riscv_cpu_cfg().
>
> Suggested-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Weiwei Li
> ---
>   target/riscv/csr.c | 32 +++++++++-----------------------
>   1 file changed, 9 insertions(+), 23 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 53f1a331f9..ffa2d7b606 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -213,9 +213,7 @@ static RISCVException any32(CPURISCVState *env, int csrno)
>   
>   static int aia_any(CPURISCVState *env, int csrno)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (!cpu->cfg.ext_smaia) {
> +    if (!riscv_cpu_cfg(env)->ext_smaia) {
>           return RISCV_EXCP_ILLEGAL_INST;
>       }
>   
> @@ -224,9 +222,7 @@ static int aia_any(CPURISCVState *env, int csrno)
>   
>   static int aia_any32(CPURISCVState *env, int csrno)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (!cpu->cfg.ext_smaia) {
> +    if (!riscv_cpu_cfg(env)->ext_smaia) {
>           return RISCV_EXCP_ILLEGAL_INST;
>       }
>   
> @@ -253,9 +249,7 @@ static int smode32(CPURISCVState *env, int csrno)
>   
>   static int aia_smode(CPURISCVState *env, int csrno)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (!cpu->cfg.ext_ssaia) {
> +    if (!riscv_cpu_cfg(env)->ext_ssaia) {
>           return RISCV_EXCP_ILLEGAL_INST;
>       }
>   
> @@ -264,9 +258,7 @@ static int aia_smode(CPURISCVState *env, int csrno)
>   
>   static int aia_smode32(CPURISCVState *env, int csrno)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (!cpu->cfg.ext_ssaia) {
> +    if (!riscv_cpu_cfg(env)->ext_ssaia) {
>           return RISCV_EXCP_ILLEGAL_INST;
>       }
>   
> @@ -380,9 +372,7 @@ static RISCVException pointer_masking(CPURISCVState *env, int csrno)
>   
>   static int aia_hmode(CPURISCVState *env, int csrno)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (!cpu->cfg.ext_ssaia) {
> +    if (!riscv_cpu_cfg(env)->ext_ssaia) {
>           return RISCV_EXCP_ILLEGAL_INST;
>        }
>   
> @@ -391,9 +381,7 @@ static int aia_hmode(CPURISCVState *env, int csrno)
>   
>   static int aia_hmode32(CPURISCVState *env, int csrno)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (!cpu->cfg.ext_ssaia) {
> +    if (!riscv_cpu_cfg(env)->ext_ssaia) {
>           return RISCV_EXCP_ILLEGAL_INST;
>       }
>   
> @@ -430,9 +418,7 @@ static RISCVException debug(CPURISCVState *env, int csrno)
>   
>   static RISCVException seed(CPURISCVState *env, int csrno)
>   {
> -    RISCVCPU *cpu = env_archcpu(env);
> -
> -    if (!cpu->cfg.ext_zkr) {
> +    if (!riscv_cpu_cfg(env)->ext_zkr) {
>           return RISCV_EXCP_ILLEGAL_INST;
>       }
>   
> @@ -555,7 +541,7 @@ static RISCVException read_vl(CPURISCVState *env, int csrno,
>   
>   static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
>   {
> -    *val = env_archcpu(env)->cfg.vlen >> 3;
> +    *val = riscv_cpu_cfg(env)->vlen >> 3;
>       return RISCV_EXCP_NONE;
>   }
>   
> @@ -610,7 +596,7 @@ static RISCVException write_vstart(CPURISCVState *env, int csrno,
>        * The vstart CSR is defined to have only enough writable bits
>        * to hold the largest element index, i.e. lg2(VLEN) bits.
>        */
> -    env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
> +    env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlen));
>       return RISCV_EXCP_NONE;
>   }
>