[PULL] Fourth RISC-V PR for QEMU 8.0, Attempt 2

[Palmer Dabbelt]

The following changes since commit 417296c8d8588f782018d01a317f88957e9786d6:

  tests/qtest/netdev-socket: Raise connection timeout to 60 seconds (2023-02-09 
11:23:53 +0000)

are available in the Git repository at:

  git@github.com:palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230224

for you to fetch changes up to 8c89d50c10afdd98da82642ca5e9d7af4f1c18bd:

  target/riscv: Fix vslide1up.vf and vslide1down.vf (2023-02-23 14:21:34 -0800)

----------------------------------------------------------------
Fourth RISC-V PR for QEMU 8.0, Attempt 2

* A triplet of cleanups to the kernel/initrd loader that avoids
  duplication between the various boards.
* Weiwei Li, Daniel Henrique Barboza, and Liu Zhiwei have been added as
  reviewers.  Thanks for the help!
* A fix for PMP matching to avoid incorrectly appling the default
  permissions on PMP permission violations.
* A cleanup to avoid an unnecessary avoid env_archcpu() in
  cpu_get_tb_cpu_state().
* Fixes for the vector slide instructions to avoid truncating 64-bit
  values (such as doubles) on 32-bit targets.

----------------------------------------------------------------
Alistair Francis (1):
      MAINTAINERS: Add some RISC-V reviewers

Daniel Henrique Barboza (4):
      hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()
      hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
      hw/riscv/boot.c: make riscv_load_initrd() static
      target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()

Frank Chang (1):
      target/riscv: Remove privileged spec version restriction for RVV

Himanshu Chauhan (1):
      target/riscv: Smepmp: Skip applying default rules when address matches

LIU Zhiwei (1):
      target/riscv: Fix vslide1up.vf and vslide1down.vf

 MAINTAINERS                  |  3 ++
 hw/riscv/boot.c              | 97 ++++++++++++++++++++++++++++----------------
 hw/riscv/microchip_pfsoc.c   | 12 +-----
 hw/riscv/opentitan.c         |  4 +-
 hw/riscv/sifive_e.c          |  4 +-
 hw/riscv/sifive_u.c          | 12 +-----
 hw/riscv/spike.c             | 14 ++-----
 hw/riscv/virt.c              | 12 +-----
 include/hw/riscv/boot.h      |  3 +-
 target/riscv/cpu.c           |  2 +-
 target/riscv/cpu_helper.c    |  2 +-
 target/riscv/csr.c           | 21 ++++------
 target/riscv/pmp.c           |  9 ++--
 target/riscv/vector_helper.c |  4 +-
 14 files changed, 98 insertions(+), 101 deletions(-)
Subject: [PULL] Fourth RISC-V PR for QEMU 8.0, Attempt 2

The following changes since commit 417296c8d8588f782018d01a317f88957e9786d6:

  tests/qtest/netdev-socket: Raise connection timeout to 60 seconds (2023-02-09 
11:23:53 +0000)

are available in the Git repository at:

  git@github.com:palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230224

for you to fetch changes up to 8c89d50c10afdd98da82642ca5e9d7af4f1c18bd:

  target/riscv: Fix vslide1up.vf and vslide1down.vf (2023-02-23 14:21:34 -0800)

----------------------------------------------------------------
Fourth RISC-V PR for QEMU 8.0, Attempt 2

* A triplet of cleanups to the kernel/initrd loader that avoids
  duplication between the various boards.
* Weiwei Li, Daniel Henrique Barboza, and Liu Zhiwei have been added as
  reviewers.  Thanks for the help!
* A fix for PMP matching to avoid incorrectly appling the default
  permissions on PMP permission violations.
* A cleanup to avoid an unnecessary avoid env_archcpu() in
  cpu_get_tb_cpu_state().
* Fixes for the vector slide instructions to avoid truncating 64-bit
  values (such as doubles) on 32-bit targets.

----------------------------------------------------------------
I've dropped the OpenSBI update from the first attempt.  I'll take a
shot at fixing it given Thomas' instructions, but since Peter said some
PRs may be processed locally I figured it'd be easier to get this out
now -- we'd probably want to pull whatever CI fixes are necessary for
OpenSBI before the bump either way, just to avoid a history breakage, so
I figure this doesn't hurt anything.

If this doesn't process then no big deal on my end, there's some more
stuff floating around.

----------------------------------------------------------------
Alistair Francis (1):
      MAINTAINERS: Add some RISC-V reviewers

Daniel Henrique Barboza (4):
      hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()
      hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
      hw/riscv/boot.c: make riscv_load_initrd() static
      target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()

Frank Chang (1):
      target/riscv: Remove privileged spec version restriction for RVV

Himanshu Chauhan (1):
      target/riscv: Smepmp: Skip applying default rules when address matches

LIU Zhiwei (1):
      target/riscv: Fix vslide1up.vf and vslide1down.vf

 MAINTAINERS                  |  3 ++
 hw/riscv/boot.c              | 97 ++++++++++++++++++++++++++++----------------
 hw/riscv/microchip_pfsoc.c   | 12 +-----
 hw/riscv/opentitan.c         |  4 +-
 hw/riscv/sifive_e.c          |  4 +-
 hw/riscv/sifive_u.c          | 12 +-----
 hw/riscv/spike.c             | 14 ++-----
 hw/riscv/virt.c              | 12 +-----
 include/hw/riscv/boot.h      |  3 +-
 target/riscv/cpu.c           |  2 +-
 target/riscv/cpu_helper.c    |  2 +-
 target/riscv/csr.c           | 21 ++++------
 target/riscv/pmp.c           |  9 ++--
 target/riscv/vector_helper.c |  4 +-
 14 files changed, 98 insertions(+), 101 deletions(-)