Re: [PATCH v5 14/14] Hexagon (target/hexagon) Improve code gen for predicated HVX instructions

[Anton Johansson]

On 1/31/23 23:56, Taylor Simpson wrote:
> The following improvements are made for predicated HVX instructions
>      During gen_commit_hvx, unconditionally move the "new" value into
>          the dest
>      Don't set slot_cancelled
>      Remove runtime bookkeeping of which registers were updated
>      Reduce the cases where gen_log_vreg_write[_pair] is called
>          It's only needed for special operands VxxV and VyV
>      Remove gen_log_qreg_write
>
> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
> ---
>   target/hexagon/cpu.h                |  5 +--
>   target/hexagon/gen_tcg_hvx.h        | 17 +-------
>   target/hexagon/translate.h          | 16 +++-----
>   target/hexagon/genptr.c             | 50 +++---------------------
>   target/hexagon/translate.c          | 60 +++--------------------------
>   target/hexagon/README               | 28 ++++----------
>   target/hexagon/gen_analyze_funcs.py |  3 +-
>   target/hexagon/gen_tcg_funcs.py     | 35 ++++-------------
>   8 files changed, 37 insertions(+), 177 deletions(-)
Reviewed-by: Anton Johansson <anjo@rev.ng>