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[PATCH v7 06/20] target/arm: Wrap arm_rebuild_hflags calls with tcg_enab
From: |
Fabiano Rosas |
Subject: |
[PATCH v7 06/20] target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled |
Date: |
Thu, 23 Feb 2023 10:08:27 -0300 |
This is in preparation to moving the hflags code into its own file
under the tcg/ directory.
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/boot.c | 6 +++++-
hw/intc/armv7m_nvic.c | 20 +++++++++++++-------
target/arm/arm-powerctl.c | 7 +++++--
target/arm/cpu.c | 3 ++-
target/arm/helper.c | 18 +++++++++++++-----
target/arm/machine.c | 5 ++++-
6 files changed, 42 insertions(+), 17 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 3d7d11f782..1e021c4a34 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -15,6 +15,7 @@
#include "hw/arm/boot.h"
#include "hw/arm/linux-boot-if.h"
#include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
#include "sysemu/sysemu.h"
#include "sysemu/numa.h"
#include "hw/boards.h"
@@ -827,7 +828,10 @@ static void do_cpu_reset(void *opaque)
info->secondary_cpu_reset_hook(cpu, info);
}
}
- arm_rebuild_hflags(env);
+
+ if (tcg_enabled()) {
+ arm_rebuild_hflags(env);
+ }
}
}
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index e54553283f..8e289051a4 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -18,6 +18,7 @@
#include "hw/intc/armv7m_nvic.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
+#include "sysemu/tcg.h"
#include "sysemu/runstate.h"
#include "target/arm/cpu.h"
#include "exec/exec-all.h"
@@ -2454,8 +2455,10 @@ static MemTxResult nvic_sysreg_write(void *opaque,
hwaddr addr,
/* This is UNPREDICTABLE; treat as RAZ/WI */
exit_ok:
- /* Ensure any changes made are reflected in the cached hflags. */
- arm_rebuild_hflags(&s->cpu->env);
+ if (tcg_enabled()) {
+ /* Ensure any changes made are reflected in the cached hflags. */
+ arm_rebuild_hflags(&s->cpu->env);
+ }
return MEMTX_OK;
}
@@ -2636,11 +2639,14 @@ static void armv7m_nvic_reset(DeviceState *dev)
}
}
- /*
- * We updated state that affects the CPU's MMUidx and thus its hflags;
- * and we can't guarantee that we run before the CPU reset function.
- */
- arm_rebuild_hflags(&s->cpu->env);
+ if (tcg_enabled()) {
+ /*
+ * We updated state that affects the CPU's MMUidx and thus its
+ * hflags; and we can't guarantee that we run before the CPU
+ * reset function.
+ */
+ arm_rebuild_hflags(&s->cpu->env);
+ }
}
static void nvic_systick_trigger(void *opaque, int n, int level)
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
index b75f813b40..326a03153d 100644
--- a/target/arm/arm-powerctl.c
+++ b/target/arm/arm-powerctl.c
@@ -15,6 +15,7 @@
#include "arm-powerctl.h"
#include "qemu/log.h"
#include "qemu/main-loop.h"
+#include "sysemu/tcg.h"
#ifndef DEBUG_ARM_POWERCTL
#define DEBUG_ARM_POWERCTL 0
@@ -127,8 +128,10 @@ static void arm_set_cpu_on_async_work(CPUState
*target_cpu_state,
target_cpu->env.regs[0] = info->context_id;
}
- /* CP15 update requires rebuilding hflags */
- arm_rebuild_hflags(&target_cpu->env);
+ if (tcg_enabled()) {
+ /* CP15 update requires rebuilding hflags */
+ arm_rebuild_hflags(&target_cpu->env);
+ }
/* Start the new CPU at the requested address */
cpu_set_pc(target_cpu_state, info->entry);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index da416f7b1c..0b333a749f 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -542,8 +542,9 @@ static void arm_cpu_reset_hold(Object *obj)
if (tcg_enabled()) {
hw_breakpoint_update_all(cpu);
hw_watchpoint_update_all(cpu);
+
+ arm_rebuild_hflags(env);
}
- arm_rebuild_hflags(env);
}
#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 07d4100365..af72e6d16c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5173,7 +5173,7 @@ static void sctlr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
/* This may enable/disable the MMU, so do a TLB flush. */
tlb_flush(CPU(cpu));
- if (ri->type & ARM_CP_SUPPRESS_TB_END) {
+ if (tcg_enabled() && ri->type & ARM_CP_SUPPRESS_TB_END) {
/*
* Normally we would always end the TB on an SCTLR write; see the
* comment in ARMCPRegInfo sctlr initialization below for why Xscale
@@ -6841,7 +6841,9 @@ void aarch64_set_svcr(CPUARMState *env, uint64_t new,
uint64_t mask)
memset(env->zarray, 0, sizeof(env->zarray));
}
- arm_rebuild_hflags(env);
+ if (tcg_enabled()) {
+ arm_rebuild_hflags(env);
+ }
}
static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -9886,7 +9888,7 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t
mask,
}
mask &= ~CACHED_CPSR_BITS;
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
- if (rebuild_hflags) {
+ if (tcg_enabled() && rebuild_hflags) {
arm_rebuild_hflags(env);
}
}
@@ -10445,7 +10447,10 @@ static void take_aarch32_exception(CPUARMState *env,
int new_mode,
env->regs[14] = env->regs[15] + offset;
}
env->regs[15] = newpc;
- arm_rebuild_hflags(env);
+
+ if (tcg_enabled()) {
+ arm_rebuild_hflags(env);
+ }
}
static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs)
@@ -11001,7 +11006,10 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
pstate_write(env, PSTATE_DAIF | new_mode);
env->aarch64 = true;
aarch64_restore_sp(env, new_el);
- helper_rebuild_hflags_a64(env, new_el);
+
+ if (tcg_enabled()) {
+ helper_rebuild_hflags_a64(env, new_el);
+ }
env->pc = addr;
diff --git a/target/arm/machine.c b/target/arm/machine.c
index fd6323f6d8..fc4a4a4064 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -871,7 +871,10 @@ static int cpu_post_load(void *opaque, int version_id)
if (!kvm_enabled()) {
pmu_op_finish(&cpu->env);
}
- arm_rebuild_hflags(&cpu->env);
+
+ if (tcg_enabled()) {
+ arm_rebuild_hflags(&cpu->env);
+ }
return 0;
}
--
2.35.3
- [PATCH v7 00/20] target/arm: Allow CONFIG_TCG=n builds, Fabiano Rosas, 2023/02/23
- [PATCH v7 01/20] target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled, Fabiano Rosas, 2023/02/23
- [PATCH v7 02/20] target/arm: Wrap TCG-only code in debug_helper.c, Fabiano Rosas, 2023/02/23
- [PATCH v7 03/20] target/arm: move translate modules to tcg/, Fabiano Rosas, 2023/02/23
- [PATCH v7 04/20] target/arm: move helpers to tcg/, Fabiano Rosas, 2023/02/23
- [PATCH v7 06/20] target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled,
Fabiano Rosas <=
- [PATCH v7 05/20] target/arm: Move psci.c into the tcg directory, Fabiano Rosas, 2023/02/23
- [PATCH v7 07/20] target/arm: Move hflags code into the tcg directory, Fabiano Rosas, 2023/02/23
- [PATCH v7 08/20] target/arm: Move regime_using_lpae_format into internal.h, Fabiano Rosas, 2023/02/23
- [PATCH v7 09/20] target/arm: Don't access TCG code when debugging with KVM, Fabiano Rosas, 2023/02/23
- [PATCH v7 10/20] cpu-defs.h: Expose CPUTLBEntryFull to non-TCG code, Fabiano Rosas, 2023/02/23
- [PATCH v7 11/20] target/arm: Move cortex sysregs into a separate file, Fabiano Rosas, 2023/02/23
- [PATCH v7 12/20] target/arm: Move 64-bit TCG CPUs into tcg/, Fabiano Rosas, 2023/02/23
- [PATCH v7 14/20] target/arm: move cpu_tcg to tcg/cpu32.c, Fabiano Rosas, 2023/02/23
- [PATCH v7 13/20] target/arm: Move aa32_max_features out of cpu_tcg.c, Fabiano Rosas, 2023/02/23
- [PATCH v7 15/20] tests/avocado: Pass parameters to migration test, Fabiano Rosas, 2023/02/23