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Re: [PATCH v3 0/2] hw/mem: CXL Type-3 Volatile Memory Support
From: |
Jonathan Cameron |
Subject: |
Re: [PATCH v3 0/2] hw/mem: CXL Type-3 Volatile Memory Support |
Date: |
Tue, 21 Feb 2023 15:32:37 +0000 |
On Tue, 21 Feb 2023 14:00:21 +0000
Jonathan Cameron <Jonathan.Cameron@huawei.com> wrote:
> v3: Noticed whilst chasing an unrelated kernel bug.
> - Drop setting of DVSEC range base addresses. Whilst harmless,
> expectation is that this will be 0 until the OS sets it (or uses
> HDM decoders instead)
>
> Based on following series (in order)
> 1. [PATCH v4 00/10] hw/cxl: CXL emulation cleanups and minor fixes for
> upstream
> 2. [PATCH v4 0/8] hw/cxl: RAS error emulation and injection
I sent these in the wrong order. Now v5 (comment change and some tags)
Other series unchanged.
> 3. [PATCH 0/2] hw/cxl: Passthrough HDM decoder emulation
>
> Based on: Message-Id: 20230206172816.8201-1-Jonathan.Cameron@huawei.com
> Based-on: Message-id: 20230217172924.25239-1-Jonathan.Cameron@huawei.com
Based-on: Message-id: 20230221152145.9736-1-Jonathan.Cameron@huawei.com
> Based-on: Message-id: 20230125152703.9928-1-Jonathan.Cameron@huawei.com
>
> Kernel code is queued up in kernel.org cxl/next for the merge window
> that just opened.
>
> Now we have some kernel code to test this against (and it looks good)
> I'd like to propose this series for upstream following 3 other series
> already proposed for inclusion:
>
> Original cover letter with minor updates.
>
> This patches provides 2 features to the CXL Type-3 Device:
> 1) Volatile Memory Region Support
> 2) Multi-Region support (1 Volatile, 1 Persistent)
>
> Summary of Changes per-commit:
> 1) Whitespace updates to docs and tests
> 2) Refactor CDAT DSMAS Initialization for multi-region initialization
> Multi-Region and Volatile Memory support for CXL Type-3 Devices
> Test and Documentation updates
>
> The final patch in this series makes 6 major changes to the type-3
> device in order to implement multi-region and volatile region support
> 1) The HostMemoryBackend [hostmem] has been replaced by two
> [hostvmem] and [hostpmem] to store volatile and persistent memory
> respectively
> 2) The single AddressSpace has been replaced by two AddressSpaces
> [hostvmem_as] and [hostpmem_as] to map respective memdevs.
> 3) Each memory region size and total region are stored separately
> 4) The CDAT and DVSEC memory map entries have been updated:
> a) if vmem is present, vmem is mapped at DPA(0)
> b) if pmem is present
> i) and vmem is present, pmem is mapped at DPA(vmem->size)
> ii) else, pmem is mapped at DPA(0)
> c) partitioning of pmem is not supported in this patch set but
> has been discussed and this design should suffice.
> 5) Read/Write functions have been updated to access AddressSpaces
> according to the mapping described in #4. Access to the
> persistent address space is calculated by (dpa-vmem_len)
> 6) cxl-mailbox has been updated to report the respective size of
> volatile and persistent memory region
>
>
> Gregory Price (2):
> tests/qtest/cxl-test: whitespace, line ending cleanup
> hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent)
>
> docs/system/devices/cxl.rst | 49 ++++--
> hw/cxl/cxl-mailbox-utils.c | 26 +--
> hw/mem/cxl_type3.c | 294 +++++++++++++++++++++++++--------
> include/hw/cxl/cxl_device.h | 11 +-
> tests/qtest/bios-tables-test.c | 8 +-
> tests/qtest/cxl-test.c | 146 +++++++++++-----
> 6 files changed, 392 insertions(+), 142 deletions(-)
>