[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH] target/ppc/translate: Add dummy implementation for dcblc ins
From: |
Bernhard Beschow |
Subject: |
Re: [PATCH] target/ppc/translate: Add dummy implementation for dcblc instruction |
Date: |
Sun, 19 Feb 2023 10:57:12 +0000 |
Am 30. Januar 2023 22:23:59 UTC schrieb Richard Henderson
<richard.henderson@linaro.org>:
>On 1/30/23 08:49, Bernhard Beschow wrote:
>> The dcblc instruction is used by u-boot in mpc85xx/start.S. Without it,
>> an illegal istruction exception is generated very early in the boot
>> process where the processor is not yet able to handle exceptions. See:
>>
>> https://github.com/u-boot/u-boot/blob/v2023.01/arch/powerpc/cpu/mpc85xx/start.S#L1840
>>
>> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
>> ---
>> target/ppc/translate.c | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
>> index edb3daa9b5..8c32e697d9 100644
>> --- a/target/ppc/translate.c
>> +++ b/target/ppc/translate.c
>> @@ -5261,6 +5261,14 @@ static void gen_dcbtls(DisasContext *ctx)
>> tcg_temp_free(t0);
>> }
>> +/* dcblc */
>> +static void gen_dcblc(DisasContext *ctx)
>> +{
>> + /*
>> + * interpreted as no-op
>> + */
>
>Missing
>
>If MSR[UCLE] (user-mode cache lock enable) is set, dcblc[e] may be performed
>while in
>user mode (MSR[PR] = 1). If MSR[UCLE] is clear, an attempt to perform this
>instructions
>in user mode causes a DSI. ESR[DLK] is set for this DSI.
>
>but that's also true for the current implementation of dcbtls. So,
>
>Acked-by: Richard Henderson <richard.henderson@linaro.org>
Ping
Does that mean it's ready to be queued or do we need a Reviewed-by as well?
>
>
>r~
- Re: [PATCH] target/ppc/translate: Add dummy implementation for dcblc instruction,
Bernhard Beschow <=