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[PULL 00/30] target-arm queue
From: |
Peter Maydell |
Subject: |
[PULL 00/30] target-arm queue |
Date: |
Thu, 16 Feb 2023 17:10:53 +0000 |
The following changes since commit 003ba52a8b327180e284630b289c6ece5a3e08b9:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2023-02-16 11:16:39 +0000)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230216
for you to fetch changes up to caf01d6a435d9f4a95aeae2f9fc6cb8b889b1fb8:
tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG (2023-02-16
16:28:53 +0000)
----------------------------------------------------------------
target-arm queue:
* Some mostly M-profile-related code cleanups
* avocado: Retire the boot_linux.py AArch64 TCG tests
* hw/arm/smmuv3: Add GBPA register
* arm/virt: don't try to spell out the accelerator
* hw/arm: Attach PSPI module to NPCM7XX SoC
* Some cleanup/refactoring patches aiming towards
allowing building Arm targets without CONFIG_TCG
----------------------------------------------------------------
Alex Bennée (1):
tests/avocado: retire the Aarch64 TCG tests from boot_linux.py
Claudio Fontana (3):
target/arm: rename handle_semihosting to tcg_handle_semihosting
target/arm: wrap psci call with tcg_enabled
target/arm: wrap call to aarch64_sve_change_el in tcg_enabled()
Cornelia Huck (1):
arm/virt: don't try to spell out the accelerator
Fabiano Rosas (7):
target/arm: Move PC alignment check
target/arm: Move cpregs code out of cpu.h
tests/avocado: Skip tests that require a missing accelerator
tests/avocado: Tag TCG tests with accel:tcg
target/arm: Use "max" as default cpu for the virt machine with KVM
tests/qtest: arm-cpu-features: Match tests to required accelerators
tests/qtest: Restrict tpm-tis-devices-{swtpm}-test to CONFIG_TCG
Hao Wu (3):
MAINTAINERS: Add myself to maintainers and remove Havard
hw/ssi: Add Nuvoton PSPI Module
hw/arm: Attach PSPI module to NPCM7XX SoC
Jean-Philippe Brucker (2):
hw/arm/smmu-common: Support 64-bit addresses
hw/arm/smmu-common: Fix TTB1 handling
Mostafa Saleh (1):
hw/arm/smmuv3: Add GBPA register
Philippe Mathieu-Daudé (12):
hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro
target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation
target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope
target/arm: Constify ID_PFR1 on user emulation
target/arm: Convert CPUARMState::eabi to boolean
target/arm: Avoid resetting CPUARMState::eabi field
target/arm: Restrict CPUARMState::gicv3state to sysemu
target/arm: Restrict CPUARMState::arm_boot_info to sysemu
target/arm: Restrict CPUARMState::nvic to sysemu
target/arm: Store CPUARMState::nvic as NVICState*
target/arm: Declare CPU <-> NVIC helpers in 'hw/intc/armv7m_nvic.h'
hw/arm: Add missing XLNX_ZYNQMP_ARM -> USB_DWC3 Kconfig dependency
MAINTAINERS | 8 +-
docs/system/arm/nuvoton.rst | 2 +-
hw/arm/smmuv3-internal.h | 7 +
include/hw/arm/npcm7xx.h | 2 +
include/hw/arm/smmu-common.h | 2 -
include/hw/arm/smmuv3.h | 1 +
include/hw/intc/armv7m_nvic.h | 128 +++++++++++++++++-
include/hw/ssi/npcm_pspi.h | 53 ++++++++
linux-user/user-internals.h | 2 +-
target/arm/cpregs.h | 98 ++++++++++++++
target/arm/cpu.h | 228 ++-------------------------------
target/arm/internals.h | 14 --
hw/arm/npcm7xx.c | 25 +++-
hw/arm/smmu-common.c | 4 +-
hw/arm/smmuv3.c | 43 ++++++-
hw/arm/virt.c | 10 +-
hw/intc/armv7m_nvic.c | 38 ++----
hw/ssi/npcm_pspi.c | 221 ++++++++++++++++++++++++++++++++
linux-user/arm/cpu_loop.c | 4 +-
target/arm/cpu.c | 5 +-
target/arm/cpu_tcg.c | 3 +
target/arm/helper.c | 31 +++--
target/arm/m_helper.c | 86 +++++++------
target/arm/machine.c | 18 +--
tests/qtest/arm-cpu-features.c | 28 ++--
hw/arm/Kconfig | 1 +
hw/ssi/meson.build | 2 +-
hw/ssi/trace-events | 5 +
tests/avocado/avocado_qemu/__init__.py | 4 +
tests/avocado/boot_linux.py | 48 ++-----
tests/avocado/boot_linux_console.py | 1 +
tests/avocado/machine_aarch64_virt.py | 63 ++++++++-
tests/avocado/reverse_debugging.py | 8 ++
tests/qtest/meson.build | 4 +-
34 files changed, 798 insertions(+), 399 deletions(-)
create mode 100644 include/hw/ssi/npcm_pspi.h
create mode 100644 hw/ssi/npcm_pspi.c
- [PULL 00/30] target-arm queue,
Peter Maydell <=
- [PULL 01/30] hw/intc/armv7m_nvic: Use OBJECT_DECLARE_SIMPLE_TYPE() macro, Peter Maydell, 2023/02/16
- [PULL 02/30] target/arm: Simplify arm_v7m_mmu_idx_for_secstate() for user emulation, Peter Maydell, 2023/02/16
- [PULL 03/30] target/arm: Reduce arm_v7m_mmu_idx_[all/for_secstate_and_priv]() scope, Peter Maydell, 2023/02/16
- [PULL 04/30] target/arm: Constify ID_PFR1 on user emulation, Peter Maydell, 2023/02/16
- [PULL 06/30] target/arm: Avoid resetting CPUARMState::eabi field, Peter Maydell, 2023/02/16
- [PULL 07/30] target/arm: Restrict CPUARMState::gicv3state to sysemu, Peter Maydell, 2023/02/16
- [PULL 05/30] target/arm: Convert CPUARMState::eabi to boolean, Peter Maydell, 2023/02/16
- [PULL 08/30] target/arm: Restrict CPUARMState::arm_boot_info to sysemu, Peter Maydell, 2023/02/16
- [PULL 09/30] target/arm: Restrict CPUARMState::nvic to sysemu, Peter Maydell, 2023/02/16
- [PULL 10/30] target/arm: Store CPUARMState::nvic as NVICState*, Peter Maydell, 2023/02/16