Re: [PATCH] target/riscv: Fix vslide1up.vf and vslide1down.vf

[Palmer Dabbelt]

On Mon, 13 Feb 2023 01:45:50 PST (-0800), zhiwei_liu@linux.alibaba.com wrote:
> vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its
> scalar input should be uint64_t to hold the 64 bits float register.And the
> same for vslide1down_##BITWIDTH.
>
> This bug is caught when run these instructions on qemu-riscv32.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> ---
>  target/riscv/vector_helper.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 00de879787..3073c54871 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -5038,7 +5038,7 @@ GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4)
>  GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8)
>
>  #define GEN_VEXT_VSLIE1UP(BITWIDTH, H)                                      \
> -static void vslide1up_##BITWIDTH(void *vd, void *v0, target_ulong s1,       \
> +static void vslide1up_##BITWIDTH(void *vd, void *v0, uint64_t s1,           \
>                       void *vs2, CPURISCVState *env, uint32_t desc)          \
>  {                                                                           \
>      typedef uint##BITWIDTH##_t ETYPE;                                       \
> @@ -5086,7 +5086,7 @@ GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, 32)
>  GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, 64)
>
>  #define GEN_VEXT_VSLIDE1DOWN(BITWIDTH, H)                                     \
> -static void vslide1down_##BITWIDTH(void *vd, void *v0, target_ulong s1,       \
> +static void vslide1down_##BITWIDTH(void *vd, void *v0, uint64_t s1,           \
>                         void *vs2, CPURISCVState *env, uint32_t desc)          \
>  {                                                                             \
>      typedef uint##BITWIDTH##_t ETYPE;                                         \

Thanks, applied to riscv-to-apply.next.