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From: | Philippe Mathieu-Daudé |
Subject: | Re: [PATCH v2 3/4] target/mips: implement CP0.Config7.WII bit support |
Date: | Thu, 16 Feb 2023 09:08:15 +0100 |
User-agent: | Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.7.2 |
On 16/2/23 06:17, Marcin Nowakowski wrote:
Some pre-release 6 cores use CP0.Config7.WII bit to indicate that a disabled interrupt should wake up a sleeping CPU. Enable this bit by default for M14K(c) and P5600. There are potentially other cores that support this feature, but I do not have a complete list. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com> --- target/mips/cpu-defs.c.inc | 3 +++ target/mips/cpu.c | 6 ++++-- target/mips/cpu.h | 1 + 3 files changed, 8 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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