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Re: [PATCH v3 02/10] target/riscv: always allow write_misa() to write MI
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v3 02/10] target/riscv: always allow write_misa() to write MISA |
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Date: |
Thu, 16 Feb 2023 08:31:58 +0800 |
On Thu, Feb 16, 2023 at 2:58 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> At this moment, and apparently since ever, we have no way of enabling
> RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
> the nuts and bolts that handles how to properly write this CSR, has
> always been a no-op as well because write_misa() will always exit
> earlier.
>
> This seems to be benign in the majority of cases. Booting an Ubuntu
> 'virt' guest and logging all the calls to 'write_misa' shows that no
> writes to MISA CSR was attempted. Writing MISA, i.e. enabling/disabling
> RISC-V extensions after the machine is powered on, seems to be a niche
> use.
>
> Regardless, the spec says that MISA is a WARL read-write CSR, and gating
> the writes in the register doesn't make sense. OS and applications
> should be wary of the consequences when writing it, but the write itself
> must always be allowed.
>
> Remove the RISCV_FEATURE_MISA verification at the start of write_misa(),
> removing RISCV_FEATURE_MISA altogether since there will be no more
> callers of this enum.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu.h | 1 -
> target/riscv/csr.c | 5 -----
> 2 files changed, 6 deletions(-)
>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
[PATCH v3 03/10] target/riscv: introduce riscv_cpu_cfg(), Daniel Henrique Barboza, 2023/02/15
[PATCH v3 05/10] target/riscv/cpu.c: error out if EPMP is enabled without PMP, Daniel Henrique Barboza, 2023/02/15
[PATCH v3 06/10] target/riscv: remove RISCV_FEATURE_EPMP, Daniel Henrique Barboza, 2023/02/15
[PATCH v3 04/10] target/riscv: remove RISCV_FEATURE_DEBUG, Daniel Henrique Barboza, 2023/02/15